5/15/2003 - Synopsys, Inc. (Nasdaq:SNPS), the world leader in integrated circuit (IC) design software, announced that ATI Research, a subsidiary of ATI Technologies, Inc., has adopted Synopsys' DFT CompilerTM SoCBIST to implement the design-for-test architecture for its upcoming next-generation visual processor. SoCBIST is an extension to DFT Compiler, a key component of Synopsys' GalaxyTM Design Platform. By using SoCBIST, ATI is able to improve test quality and reduce test cost for one of their most important designs.
ATI's visual processing unit (VPU) has more than 200 million transistors of digital logic. A design of this size and complexity requires not only extremely high stuck-at fault coverage, but also thorough testing for delay-related defects, the preponderant defect type in 0.13 micron process geometries and below. Using basic scan methods, excellent delay test requires up to 6X more tester time than required for stuck-at faults, which already is at an unacceptable cost of test.
"Synopsys SoCBIST's deterministic logic BIST capability allows us to reach a quality/cost tradeoff that we could not attain with any other alternative," said Robert Feldstein, vice president of engineering, ATI Research. "We required an entirely new test approach to achieve our strict quality objectives for our new VPUs at an acceptable cost of test. In addition, because of our aggressive time-to-market goals, we needed a test solution that would not jeopardize our design schedule. Synopsys SoCBIST gave us at least an order-of-magnitude leeway to implement the increased testing we desired, and any schedule risk is minimized because SoCBIST is a straightforward extension to familiar Synopsys design flows."
"Faced with the unprecedented test challenges of this huge design, ATI selected Synopsys SoCBIST to improve test quality and reduce test cost for its next-generation visual processors," said Antun Domic, senior vice president and general manager of Synopsys' Nanometer Analysis and Test business unit. "SoCBIST is focused on enabling our customers to meet the toughest quality and cost objectives, and working with ATI provides further validation of our solution and commitment in this critical area."
Synopsys Versatile Test Solutions
Synopsys offers a complete line of integrated products and services to meet demanding manufacturing test requirements. The company's award-winning design-for-test offering includes the advanced DFT Compiler and TetraMAX(R) ATPG tools. An integral part of the Synopsys Galaxy Design Platform, DFT Compiler incorporates the latest generation of Synopsys' patented 1-pass test synthesis technology and enables design teams to more efficiently meet their DFT closure goals. TetraMAX complements scan-based test methodologies by providing industry-leading ATPG performance, capacity and ease of use. DFT Compiler SoCBIST provides deterministic logic BIST capabilities and enables designers to significantly lower test costs with substantial test time and data volume reduction, while retaining scan's very high fault coverage. Complementing its test products, Synopsys offers comprehensive test services delivered by its world-class team of DFT experts.
Synopsys, Inc. (Nasdaq: SNPS) is the world leader in electronic design automation (EDA) software for integrated circuit (IC) design. The company delivers technology-leading IC design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/.
Synopsys is a registered trademark of Synopsys, Inc. DFT Compiler and Galaxy are trademarks of Synopsys.
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