5/15/2003 - Cadence Design Systems, Inc. (NYSE: CDN), announced that Cadence(R)RTL Compiler(TM) helped Teradiant Networks Inc. accelerate the development of its TeraPacket chipset, which comprises a network processing engine and traffic manager. The more than 200-million-transistor chipset has been deemed to be among the densest semiconductors designed to date.
It took Teradiant eight months to design TeraPacket(TM) using Cadence RTL Compiler, a high-speed, high-capacity tool for register transfer level (RTL) synthesis of multi-million-gate integrated circuits (ICs) targeting advanced foundry process technology. Cadence RTL Compiler's breakthrough global-focus algorithms enabled improved speed and die area, with significant enhancements in runtime and memory consumption over other market solutions.
"Teradiant's work with RTL Compiler enabled the design of TeraPacket," said Satchit Jain, chief executive officer of Teradiant Networks. "RTL Compiler helped us meet the demand by networking equipment OEMs for high-ROI enabling semiconductors that will drive the growth of next-generation Internet routers, multi-service switches and metropolitan switches. Teradiant's aggressive design goals led us to select Cadence as our design automation partner."
"Having defined a chip architecture that delivers flexibility, high performance, and significantly reduced time-to-market, Teradiant Networks has demonstrated its leadership in the network processor segment," said Ping Chao, senior vice president and general manager of the Encounter platform at Cadence. "We are delighted that Teradiant worked with us to build this remarkable chipset."
Cadence purchased RTL Compiler with its recent acquisition of Get2Chip.
About Teradiant Networks
Teradiant Networks develops and markets semiconductors that enable networking system manufacturers to build scalable switch and router platforms for next-generation networks. Analysts predict a sustainable compound annual growth rate of over 60% for these components, leading to projected industry revenues of over $1 billion by 2005. Teradiant chipsets are designed to overcome the performance, scalability and deployment limitations of today's network processors and of custom-designed ASICs used for packet processing and traffic management. In February 2001, Teradiant raised over $26 million in first-round funding from Menlo Ventures, Idanta Partners, Diamondhead Ventures, FBB, Compass Technology Partners, and private investors. For more information, visit www.teradiant.com or call 408-519-1700.
Cadence is the world's leader in electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,200 employees and 2002 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.
Cadence, the Cadence logo and RTL Compiler are registered trademarks of Cadence Design Systems, Inc.
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