5/14/2003 - Mentor Graphics Corporation (Nasdaq: MENT) announced an innovation in parallel processing, MTflex, for the Calibre® design-to-silicon platform. MTflex delivers cost-effective access to the high-performance compute power needed to manage the design-to-silicon flow in nanometer design. This flow includes physical verification, parasitic extraction, design for manufacturability (DFM), resolution enhancement technologies (RET) and mask data preparation (MDP). In initial evaluations, Mentor experienced a greater than 60 percent drop in the cost for a typical compute configuration by using MTflex.
MTflex makes Calibre a fourth-generation hierarchical data processing engine that brings multi-threaded hierarchical, parallel processing to a networked compute environment. MTflex allows designers to gain significant performance improvements while taking simultaneous advantage of large SMP servers and/or low-cost network processors such as rack-mount systems. For design teams using the comprehensive Calibre design-to-silicon platform, there are added benefits when MTflex is applied to all Calibre applications.
Several challenges surface in nanometer design-an exponential increase in total geometric shape count, a sharp rise in the number and complexity of design rules, and requirements for post-layout modifications such as planarization fill, OPC or scattering bars to ensure manufacturability. All of these factors contribute to an explosion in both design database size, and the number of post-layout operations required. This demands a high-performance compute environment.
On a parallel track, the cost for a compute infrastructure capable of verifying nanometer designs is increasing significantly. With this in mind, design teams look for ways to reduce the cost associated with nanometer design, while maintaining or accelerating time to market.
To combat these rising costs, Mentor has extended Calibre's MT (multi-threaded) hierarchical data processing engine to take advantage of multi-threaded processing in a networked compute environment where small threads of physical data can be easily managed by inexpensive and fast 32-bit remote machines. Design teams can access this capability using existing hardware or by purchasing additional inexpensive hardware to create high-performance, cost-effective rack-mount compute environments.
MTflex delivers considerable benefits for IC design teams because the design's hierarchical data structure is maintained. Unlike other approaches that must flatten design data or explode cell counts by orders of magnitude to exploit a distributed environment, MTflex preserves the hierarchy algorithms that allow the Calibre MT technology to retain the design database's hierarchy. By maintaining hierarchy, the chance of breaking, overwhelming or hampering the handoff to downstream tasks is minimized, and modifications such as resolution enhancement techniques (RET) and design for manufacturability (DFM) optimizations can be implemented efficiently.
Maintaining hierarchy is also critical to managing mask cost. With the rise in shape count and layout complexity due to RET, mask shops are under extreme pressure to control the cost of masks for nanometer designs. The advanced parallel processing achieved with MTflex allows mask shops to achieve rapid cycle times.
"MTflex is a revolutionary advancement in technology that is critical in enabling the transition to a design-to-silicon environment," said Joe Sawicki, general manager for the Mentor Graphics design-to-silicon division. "In addition, when run in a networked environment, MTflex has the potential to achieve performance comparable to a multiple-CPU workstation at one third the hardware cost."
The Calibre Design-to-Silicon Platform
In nanometer design, the handoff between IC layout and manufacturing has changed. In previous technologies, the handoff was a simple DRC/LVS check at tapeout. Now it is a multi-step process where the layout database is modified so the design can be manufactured. This presents a host of challenges. Issues arise concerning process effects, photolithography, data volumes, mask costs and acceptable yield.
To meet these challenges with confidence, design teams turn to the integrated Calibre design-to-silicon platform, which includes physical verification, full-chip, transistor-level parasitic extraction, design for manufacturability (DFM), resolution enhancement technologies (RET), and mask data preparation (MDP). The Calibre platform efficiently and accurately manages every facet of the design-to-silicon transition.
In a continuing tradition of delivering advanced technology, the Calibre design-to-silicon platform of integrated tools is recognized as the industry standard worldwide to address the complexities of the nanometer era.
The Calibre platform with MTflex capabilities will be available in Q3, 2003. Calibre customers interested in accessing MTflex in their existing Calibre suite should contact their salesperson. The MTflex capability is an enhancement to existing Calibre products under maintenance; there is no additional charge.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $600 million and employs approximately 3,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.
Mentor Graphics and Calibre are registered trademarks of Mentor Graphics Corporation.
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