5/13/2003 - Synopsys, Inc. (Nasdaq:SNPS), the world leader in integrated circuit (IC) design software, announced MagellanTM, a new hybrid formal verification product. Magellan combines new, advanced formal engines with the strengths of the built-in VCSTM simulation engine to help engineers uncover bugs that may be buried thousands of cycles deep in the design. Magellan's unique hybrid architecture is designed to handle multi-million-gate designs and provide deterministic results that are free of false-negative errors. The addition of Magellan strengthens the Synopsys DiscoveryTM Verification Platform by enabling hierarchical verification, a powerful design-for-verification (DFV) technique that allows reuse of design assumptions and assertions. Magellan supports Verilog and VHDL designs and is architected to work with the emerging SystemVerilog standard.
"NVIDIA Corporation is a market leader in visual computing technology dedicated to creating the highest quality products for our customers. We use Magellan to perform extensive block-level verification to find bugs early and with high accuracy when developing NVIDIA® graphics processing units (GPUs)," said Gopal Solanki, vice president of hardware engineering at NVIDIA. "Using Magellan we are able to reduce the overall cost of verification. We are impressed by the tool's high capacity and performance and NVIDIA relies on it to verify complex assertions on many advanced designs."
Magellan's hybrid architecture enables the tool to apply formal techniques on large, multi-million-gate designs. This architecture finds bugs by uniquely combining VCS' ability to reach deep into the design with the formal engines' ability to perform advanced mathematical analysis. The built-in VCS and formal engines adaptively and transparently leverage each other, saving time and iterations by enabling designers to uncover complex bugs that may be buried tens of thousands of cycles deep in the design.
"ST is an industry leader in creating advanced SoCs of the highest quality standard for a variety of markets," said Umberto Rossi, Formal Verification Manager at STMicroelectronics' Central R&D. "We have been an early customer of Magellan and we are successfully using it on many of our next-generation consumer and automotive product designs. By using Magellan, our engineers have found a number of deep corner-case bugs on our million-gate designs and we have consistently realized higher verification productivity."
Magellan is designed to further raise verification productivity by eliminating false-negative error reports and delivering deterministic results. Unlike traditional register transfer level (RTL) formal verification tools, Magellan helps ensure that violations detected by its formal engines can be reproduced in real-life simulation by verifying them with the built-in VCS engine before reporting the violation.
With the addition of Magellan, the Synopsys Discovery Verification Platform now enables hierarchical verification, a powerful DFV technique where block-level assumptions and assertions are automatically reused as chip-level monitors by VCS and Vera®. This ability to perform hierarchical verification within a unified verification platform helps ensure thorough verification of design assumptions and improves the designer's overall verification productivity and quality.
"The innovative hybrid architecture in Magellan reduces verification cost and time by finding complex design bugs early in the verification cycle," said Manoj Gandhi, senior vice president and general manager of the Verification Technology Group at Synopsys. "By combining the strength of our industry-leading VCS HDL simulator and Vera testbench automation tool with formal analysis techniques, we continue to advance our Discovery Verification Platform and address our customers verification needs."
Magellan is currently deployed at select customer sites on a controlled-availability basis. General availability is planned for calendar Q4, 2003. Pricing for Magellan begins at $73,500 U.S. list for a one-year technology subscription license.
About Discovery Verification Platform
The Discovery Verification Platform is a unified environment that provides high performance and efficiency of interaction among all platform components, including mixed-HDL simulation, mixed signal, system-level verification, assertions, verification intellectual property, code coverage, functional coverage, testbenches and formal analysis. The Discovery Verification Platform includes Synopsys' VCS HDL simulator, VCS MX mixed-HDL simulator, CoCentric® System Studio for system-level verification, LEDA® programmable RTL checker, Vera testbench automation tool, Magellan hybrid RTL formal verification, DesignWare® verification IP, Formality® equivalence checker, NanoSimTM and HSPICE® for mixed-signal simulation. Combined with SystemVerilog and Synopsys' design-for-verification methodology, the Discovery Verification Platform helps designers achieve higher levels of verification productivity by contributing to first-time silicon success within required project cycles.
Synopsys, Inc. (Nasdaq: SNPS) is the world leader in electronic design automation (EDA) software for integrated circuit (IC) design. The company delivers technology-leading IC design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, Calif., and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/.
Synopsys, Vera, CoCentric, HSPICE, DesignWare and Formality are registered trademarks of Synopsys, Inc. VCS, Discovery, Magellan, and NanoSim are trademarks of Synopsys, Inc.
Previous Page | News by Category | News Search
If you found this page useful, bookmark and share it on: