4/25/2003 - Altera Corporation (NASDAQ: ALTR) will present "Design Guidelines for Optimal Results in High-Density FPGAs" at the International Mentor Users Group (MUG) conference next week in San Jose, Calif. The session will review FPGA design practices that result in improved timing performance, logic utilization, and system reliability. Design engineers attending this session will learn how to minimize problems when retargeting a design to different speed grades or device architectures.
The presentation is part of Tuesday's session on FPGA Design.
Presentation: Tuesday, April 29 at 1:30 p.m.
Conference: April 28 - 30, 2003
The San Jose Room
San Jose Doubletree Hotel
2050 Gateway Place
San Jose, Calif. 95110
For More Information: www.mentorug.org/conferences/2003/
Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries.
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