Synopsys Names New Technology Fellow

4/25/2003 - Synopsys Inc. (Nasdaq: SNPS), the world leader in integrated circuit (IC) design software, announced that Tom Williams has been named a Synopsys Fellow. This award of distinction acknowledges the contributions Dr. Williams has brought to Synopsys, the influence he has had on the company's technical direction, and the role he has played in executing and delivering design for test (DFT) technology innovation to customers.

"A Synopsys Fellow is a rare individual who has reached the highest level of technical expertise and innovation, and has applied this expertise to further his or her field," said Raul Camposano, chief technology officer at Synopsys. "Tom has helped shape the direction of Synopsys test automation products. His expertise in the areas of DFT, test generation, fault simulation, synthesis and fault-tolerant computing has contributed greatly to Synopsys' leadership in test automation and has had significant positive impact on our company and on our extended community of customers."

As a member of Synopsys' test automation research and development group, Tom Williams has contributed to an impressive array of patented technologies and methodologies that have been incorporated into Synopsys' DFT CompilerTM and TetraMAX® products, including integration with Physical Compiler®, links to test equipment to enhance diagnostic capabilities, and the recently introduced DFT Compiler SoCBIST.

Tom Williams has served as founder, chair and distinguished speaker for a number of IEEE and IEEE Computer Society events and technical committees. An accomplished writer and educator, Dr. Williams has contributed to numerous technical books and papers in the area of test, is an adjunct professor at the University of Colorado in Boulder, and has served as a guest professor and Robert Bosch Fellow at the Universitaet of Hannover in Hannover Germany (1985-1997). He was named an IEEE Fellow in 1988 for leadership and contributions in DFT, and in 1989 was co-awarded the IEEE Computer Society's prestigious W. Wallace McDowell Award for the development of level-sensitive scan test for solid-state logic circuits and for leadership in the area of DFT.

Prior to joining Synopsys, Dr. Williams was with IBM's Microelectronics Division in Boulder, Colorado, where he managed the VLSI Design for Testability group. He received a BSEE from Clarkson University, an MA in pure mathematics from the State University of New York at Binghamton, and a Ph.D. in electrical engineering from Colorado State University.

Synopsys Fellows are an elite group that currently consists of seven members. Dr. Williams joins these distinguished peers: Dr. Robert Damiano, Mr. Brent Gregory, Mr. Will Naylor, Dr. Tony Ma, Mr. Ping-San Tzeng and Mr. John Waicukauski. A Fellow personifies the technical excellence that is so vital to the industry and to Synopsys in particular.

About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the world leader in electronic design automation (EDA) software for integrated circuit (IC) design. The company delivers technology-leading IC design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has more than 60 offices throughout North America, Europe, Japan and Asia. Visit Synopsys online at

Synopsys, TetraMAX and Physical Compiler are registered trademarks of Synopsys, Inc. DFT Compiler is a trademark of Synopsys.

Previous Page | News by Category | News Search

If you found this page useful, bookmark and share it on: