Synopsys' PrimeTime Sets New Timing Sign-Off Standard In the Galaxy Design Platform

4/25/2003 - Synopsys, Inc. (Nasdaq: SNPS), the world leader in integrated circuit (IC) design software, announced that the latest release of PrimeTime® -- the timing backbone in Synopsys' GalaxyTM Design Platform -- has set a new standard for performance in static timing analysis and sign-off of multimillion-gate designs. Customer benchmarks show an average of 2X and up to 7X runtime improvement over previous releases, resulting in increased designer productivity and rapid timing sign-off. PrimeTime's significant performance gains are the result of algorithmic improvements to reporting and standard delay file (SDF)-based timing analysis.

"The complexity of our graphics and core logic designs has tripled over the last three years and increased our runtime demands on PrimeTime," said Wilson Wang, director of SiS' Design Technology Development. "With the PrimeTime 2003.03 release, we verified our latest Xabre 600 high-performance graphics chip -- an eight-million gate design -- in two hours, which was a 2X improvement over previous releases. This performance gain enables our designers to achieve timing sign-off in hours instead of days and meet our aggressive time-to-market goals."

"NEC Electronics creates multimillion-gate SoC designs that require efficient timing analysis with PrimeTime," said Toshiaki Machida, senior manager, Design Strategy Group, 2nd System LSI Div., 2nd Business Development Operations Unit at NEC Electronics Corporation. "On a five million-gate design, PrimeTime 2003.03 completed analysis in 1 hour 15 minutes -- a 3X improvement over the previous release. PrimeTime continues to be an integral part of our design solution, accelerating the turnaround time for our complex SoCs."

"Renesas Technology Corp. (established on April 1, 2003 as a semiconductor joint venture between Hitachi, Ltd. and Mitsubishi Electric Corporation) develops complex SoCs for mobile, network, automotive, and digital consumer applications in the ubiquitous network society," said Mr. Hisaharu Miwa, department manager of EDA Technology Development Dept. in Design Technology Division, LSI Product Technology Unit at Renesas Technology Corp. "On our latest multimillion-gate SoC with multiple clock domains and complex timing constraints, PrimeTime2003.03 delivered a 7X runtime improvement compared to the previous release. This performance improvement enables us to speed timing sign-off of our complex designs."

As the timing backbone in Synopsys' Galaxy Design Platform, PrimeTime offers full-chip, gate-level static timing analysis together with an integrated delay calculator and advanced modeling capabilities for efficient and accurate timing signoff.

"PrimeTime continues to push the technology envelope and deliver high performance and accuracy to address customers' critical timing verification challenges," said Antun Domic, senior vice president and general manager, Synopsys' Nanometer Analysis and Test business unit. "Offered within our Galaxy Design Platform, PrimeTime now enables overnight sign-off of 50-million gate designs."

About Galaxy Design Platform
Anchored by Synopsys' Design Compiler®, AstroTM and PrimeTime, Galaxy Design Platform helps reduce design times, decrease integration costs and minimize the risks inherent in advanced, complex IC design. Galaxy Design Platform integrates Synopsys' industry-leading IC implementation tools and intellectual property (IP), including Design CompilerTM, DFT CompilerTM, Power CompilerTM, DesignWare®, Floorplan CompilerTM, Physical CompilerTM, Astro, PrimeTime, TetraMAX®, Star-RCXTTM, HerculesTM and ProteusTM.

About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is the world leader in electronic design automation (EDA) software for integrated circuit (IC) design. The company delivers technology-leading IC design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and is located in more than 60 offices throughout North America, Europe, Japan and Asia. Visit Synopsys online at

Synopsys, DesignWare, PrimeTime and TetraMAX are registered trademarks of Synopsys, Inc. Astro, Design Compiler, DFT Compiler, Physical Compiler , Floorplan Compiler, Galaxy, Hercules, Power Compiler, Proteus and Star-RCXT are trademarks of Synopsys, Inc.

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