EEMBC Confirms Breakthrough Clock Speed for TI's Highest Performance DSPs

4/25/2003 - Delivering an objective and detailed measure of performance to designers, Texas Instruments (TI) (NYSE: TXN) announced that benchmark scores for its new 720 MHz digital signal processors (DSP) were published by EEMBC, the Embedded Microprocessor Benchmark Consortium.

The 720 MHz TMS320C6416 was evaluated utilizing the EEMBC Telecom benchmarks that represent typical telecom device tasks. Three categories of benchmark tests were run and certified by the EEMBC Certification Labs. In an out-of-the-box C-compiler test, the TMS320C6416 achieved a score of 19.5 Telemarks, comparing very favorably with standard RISC processors. But the real benefits of this highly-parallel architecture show up after employing C-level optimizations, where the score jumped to 379.1 Telemarks, and in assembly-optimized tests, the device achieved a score of 628.6 Telemarks.

According to Markus Levy, EEMBC president, the TMS320C6416 is the highest performing general-purpose DSP ever benchmarked by the consortium.

"TIs spectacular achievement with the TMS320C6416 is readily apparent when we compare scores for this device with the previous-generation TMS320C6203, which was one of the first chips for which EEMBC benchmarks were published," Levy said. "The new 720-MHz chip shows a nearly three-fold improvement in its out-of-the-box score, while the optimized scores show an approximate 9X improvement."

The 720 MHz TMS320C6416 includes a foundation of eight parallel functional units, one Megabyte (MB) of on-chip high-speed memory and high-speed peripherals that accelerate applications and processing of real-time data. A 64-channel enhanced direct memory access (EDMA) controller delivers input/output efficiency that manages data transfer from system memory at gigabytes per second. In addition, three multi-channel buffered serial ports (McBSPs) each support 128 time-division multiplex (TDM) channels as well as AC97 and IIS audio interfaces. The device also features on-board Viterbi and Turbo coprocessors to further improve the channel capacity of 3G wireless basestations.

"With the aid of the EEMBC Certification Labs, the EEMBC benchmarks have provided TI with a great opportunity to independently demonstrate the superb performance of our enhanced VLIW DSP processor," said Jackie Brenner, DSP technical benchmarks manager, TI. "These benchmark scores provide an indication to our customers of how well the TMS320C64x processors handle a variety of general-purpose DSP algorithms."

The TMS320C6416 was measured against the EEMBC Telecom benchmarks, which is a suite of five algorithms that represent device performance in real-world applications. They include autocorrelation, fixed-point bit allocation, fixed point complex Fast Fourier Transform, Viterbi GSM decoder, and convolutional encoder benchmarks for which individual scores with several data sets are rendered in iterations per second.

"The code size required for most of the telecom benchmark algorithms is smaller in the TMS320C6416 than in the previous-generation TMS320C6203, with efficient new single-instruction-multiple-data (SIMD) instructions that use less system memory," said Levy.

Detailed benchmark scores on the TMS320C6416 are available at and

Previous Page | News by Category | News Search

If you found this page useful, bookmark and share it on: