Astek Develops Partitioning Tool for Atmel-based ASIC Design Validation

4/25/2003 - Atmel® Corporation (Nasdaq: ATML) and Astek Corporation will demonstrate a new partitioning tool developed by Astek for rapid validation of Atmel's platform-based ASIC designs. Astek's Advanced Partitioning Tool (APART) allows customers to implement their design without making RTL modifications and automatically preserves design hierarchy, creating a significant time-to-market advantage. With this combination of APART and Atmel's platform-based design flow, customers can expect to complete and validate their ASIC designs in less than four months.

APART is a software tool that enables a designer to automatically partition a large design done in RTL into smaller entities that can be targeted to FPGAs or off-the-shelf components. In performing the partitioning, it preserves the design hierarchy and creates all of the necessary interconnect between the smaller entities to ensure there is identical functionality to the original design. APART and any FPGA-based development platform is the one-two punch that allows ASIC designers to verify their RTL code in hardware in a matter of days. This combination of hardware and software gives ASIC designers confidence that their ASIC prototype functionality is identical to their final ASIC functionality. Firmware and application software development can start months before silicon is started and can be used to optimize the hardware logic prior to tape out.

"This combination of Atmel's standard hardware platforms with validated IP and Astek's APART software puts FPGA prototyping back as a milestone in the schedule, rather than a project in itself," commented Jay Johnson, Director of North American ASIC/ASSP Marketing for Atmel Corporation. Atmel and Astek announced a strategic partnership committed to helping customers get to market with a first pass success in the fall of 2002. Bundling Astek's Application Testing and Total Emulation of System Technology (ATTEST(TM)) and Atmel's system-on-chip devices is the focus of this effort. ATTEST is a hardware emulation and verification process methodology that can perform up to three levels of verification prior to a hard silicon commitment.

Details on pricing and availability will be provided with any new ASIC design quote from Astek. Atmel Corporation and Astek continue to develop their strategic partnership committed to helping ASIC customers get to market in record time with first-pass success.

About Atmel
Founded in 1984, Atmel Corporation is headquartered in San Jose, California with manufacturing facilities in North America and Europe. Atmel designs, manufactures and markets worldwide, advanced logic, mixed-signal, nonvolatile memory and RF semiconductors. Atmel is also a leading provider of system-level integration semiconductor solutions using CMOS, BiCMOS, SiGe, and high-voltage BCDMOS process technologies.

About Astek
Astek Corporation is a rapidly growing company providing Application Specific Integrated Circuits (ASIC), Field Programmable Gate Arrays (FPGA), board level, software, and firmware design services. Located in the shadow of Pikes Peak in Colorado Springs, Colorado, we are committed to providing top-quality services ranging from augmentation of engineering staff to turnkey solutions.

Atmel and the Atmel logo are registered trademarks of Atmel Corporation. APART is a trademark of Astek.

Atmel's ASIC product information may be retrieved at For more information on Astek please visit

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