Sequence Design Offers Hands-on Power-aware Design Tutorial at DAC

3/31/2003 - Sequence Design, the technology leader for power-aware design, is front and center at this year's DAC, thanks to the conference's emphasis on the critical importance of power issues.

Dr. Steve McCormick, Sequence's chief architect; and Jerry Frenkil, Sequence vice president of advanced development, present a three-hour "hands-on" tutorial detailing strategies for handling signal and power integrity in nanometer designs. The tandem will present a detailed overview of the issues, along with a description of automated detection and correction methods. For more information: 87256CE9006FDD42?opendocument (Due to the length of this URL, it may be necessary to copy and paste this hyperlink into your Internet browser's URL address field.)

Frenkil surfaces again on Tuesday, June 3, as part of a very seasoned panel of experts addressing the issue: "Reshaping EDA For Power." His colleagues on the panel include a "Who's Who" of power authorities, including Prof. Jan Rabaey, Prof. Dennis Sylvester, Dr. Takayasu Sakurai, and other notables. For more information:

New Products For Power
The company expects heavy traffic on both the exhibit floor and its demos, as Sequence unveils a host of new and innovative products relating to power.

A prime example is CoolTime, analyzing the electrical effects of power, voltage drop, timing, and signal integrity concurrently, reducing runtimes as much as 75 percent. Its instantaneous current analysis accounts for dynamic effects resulting from power-grid capacitance, package inductance, and on-chip decoupling capacitors.

To be added to the list for future DAC announcements from Sequence, interested parties may contact:

NanoCool Initiative
Sequence has assembled the elements of a low-power/low-voltage flow spanning architectural, logical, and physical design to respond to the challenges of nanometer design under its NanoCool initiative, a partnership between semiconductor designers, EDA tool vendors, IP companies, and library suppliers, to offer a complete flow linking power management together with timing and signal integrity for rapid design closure.

The initiative has produced a low power/low voltage design flow capable of identifying potential problems caused by power consumption and power distribution, fixing them, and validating the fixes before tape out.

Sequence's leadership position in power, noise and timing optimization, and high accuracy extraction form the foundation for this initiative. On top of this foundation Sequence is building the next generation of EDA capabilities which are specifically targeted at low-voltage, nanometer problems such as minimization of both dynamic and leakage currents, noise margin analysis and optimization, and reliability verification. The overall focus of Sequence's efforts is the concurrent analysis and optimization of power, timing, and noise. The initiative includes both high-level prediction and optimization, coupled with successive refinements and optimizations at lower levels to help designers achieve design closure.

The key components of the NanoCool flow are:

About Sequence
Sequence Design, Inc., the SoC Design Closure Company(SM), enables system-on-chip designers to bring higher-performance and lower-power integrated circuits quickly to fabrication. Sequence's power and signal integrity software give its more than 100 customers the competitive advantage they need to excel in aggressive technology markets, despite demanding complexity and time-to-market issues of nanometer design.

Sequence has worldwide development and field service operations. The company was recently named by Reed Electronics as one of the top 50 companies to watch in the electronics industry. Sequence is privately held. Sequence is a member of Cadence Design Systems' Connections(TM) and Mentor Graphics' Open Door(TM) partnership programs. Additional information is available at

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