3/25/2003 - Cypress Semiconductor Corporation (NYSE:CY) announced the availability of its MetroLink2T-2TM (CYL2T0201) link-layer device (LLD) — the first LLD on the market to offer transparent generic framing procedure (GFP-T). MetroLink2T-2 LLD is an intellectual property (IP) core that enables efficient mapping of packet data over synchronous data transmission on optical media (SONET) backbones.
The Cypress GFP-T transport core supports two channels of Gigabit Ethernet (GbE), Fibre Channel, Enterprise Systems Connection (ESCON), Fibre Connectivity (FICON), or any combination of protocols over SONET. In addition, Cypress has leveraged its virtual concatenation (VC) expertise along with GFP-T features for efficient bandwidth management.
The introduction of MetroLink2T-2 LLD demonstrates Cypress’s commitment to providing its customers with complete solutions for building communications linecards. By teaming MetroLink2T-2 LLD with other Cypress transport products — POSIC2GVCTM OC-48/STM-16 Framer, HOTLink IITM transceiver, No Bus LatencyTM (NoBLTM) synchronous SRAM, ComLinkTM bus interface, and programmable clocks — the entire linecard datapath incorporates Cypress’s products, forming a seamless system solution and eliminating the need for additional external logic.
“By adding the MetroLink LLD family to our data communications product portfolio, we are able to provide a complete solution for the packet-over-SONET transport problem,” said Christopher Norris, vice president of Cypress’s data communications division. “Our system-level solution is logically partitioned for easy design migration. This allows our customers to develop derivative linecards while re-using portions of the design, thereby significantly reducing design time, time-to-market and cost.”
The MetroLinkTM Family
MetroLink2T-2 LLD is the first member of Cypress’s MetroLink LLD family of link-layer products. MetroLink2T-2 LLD is also the first product to support GFP-T at OC-48/STM-16 rates. GFP-T is a way to encapsulate any protocol for transport over a SONET/SDH network. Using the MetroLink2T-2 LLD with GFP-T, a carrier can efficiently transport any data over standard SONET/SDH networks with no degradation of service, no waste of bandwidth, and no additional FPGAs or external logic.
The POSIC2GVC Framer
The POSIC2GVC OC-48/STM-16 framer is a revolutionary product able to provide virtual concatenation per ITU G.707. Using VC, the product enables efficient bandwidth utilization and dynamic bandwidth allocation. Furthermore, embedded packet preclassification functions allow increased packet processing, quality of service (QoS) control, and queue management performance. In addition, POSIC2GVC also transports asynchronous transfer mode (ATM) cells across SONET networks.
HOTLink II Physical-Layer Devices
The HOTLink II family of physical-layer devices offers the industry’s most flexible transceivers, with advanced features such as the widest operating range (0.2-1.5 Gbps), channel-to-channel and chip-to-chip channel bonding, by passable 8B/10B encoding, redundant dual outputs, and up to 100K gates of programmable logic. This successful family of devices includes single-channel, dual-channel, quad-channel, independent channel, and Gigabit Ethernet/Fibre Channel versions.
No Bus Latency (NoBL) SRAM
NoBL synchronous SRAMs have an architecture optimized for the most demanding high-speed applications requiring maximum bus bandwidth, such as networking, test and measurement instrumentation, video, and simulation. Available in both flow-through and pipelined versions, they eliminate the latency (dead cycles or wait states) found in conventional synchronous burst SRAM architectures when transitioning between write and read operations. By contrast, the NoBL architecture allows data transfer on every clock cycle regardless of whether a write or read operation is taking place, thereby providing 100% bus utilization.
ComLink Bus Interface and Backplane Chips
The ComLink series operates at data transfer rates up to 1.6 Gbps and includes multiplexed-differential line drivers that provide redundant links for serial backplanes, 20-bit wide, three-state buffers, and clock distribution buffers with fanouts of 1:10, 1:8 and 1:4. These devices offer configurable inputs that match industry-standard interfaces including low-voltage CMOS (LVCMOS), low-voltage differential signaling (LVDS), and regular differential (complementary I/O signal pair). The LVDS output drivers are configurable to support standard drive (1.2-ns rise and fall times) and high drive (less than 500-ps rise and fall times).
Programmable timing solutions combine the convenience of field programmability with the high performance customers have come to expect from Cypress's timing products — at a cost that is competitive with custom clocks at equivalent volumes. Not only can designers select output frequencies, our CyClocksTM and CyClocksRTTM software also enables users to optimize device parameters such as drive strength, phase-locked loop bandwidth, and crystal input capacitive loading so that each programmed device can be optimized for a specific board layout.
Product Availability and Pricing
The MetroLink2T-T (CYL2T0201) netlist is available now starting at $20,000. The CYL2T0201 source code is also available for an additional cost. The complete Cypress GFP-T transport solution, including all components, is in production now. Contact Cypress sales representatives near you for further information on pricing and solution documentation. For more information, go to the Cypress website at http://www.cypress.com/products/datasheet.cfm?partnum=CYL2T0201-AIP.
Cypress Semiconductor Corporation (NYSE: CY) is Connecting From Last Mile to First MileTM with high-performance solutions for personal, network access, enterprise, metro switch, and core communications-system applications. Cypress ConnectsTM using wireless, wireline, digital, and optical transmission standards, including USB, Fibre Channel, SONET/SDH, Gigabit Ethernet, and DWDM. Leveraging its process and system-level expertise, Cypress makes industry-leading physical layer devices, framers, and network search engines, along with a broad portfolio of high-bandwidth memories, timing technology solutions, and programmable microcontrollers. More information about Cypress is accessible online at www.cypress.com.
Cypress and the Cypress logo are registered trademarks of Cypress Semiconductor Corporation. MetroLink, MetroLink2T-2, ComLink,HOTLink, HOTLink II, POSIC2GVC, No Bus Latency, NoBL, CyClocks, CyClocksRT,“Connectivity From Last Mile to First Mile,” and “Cypress Connects” are trademarks of Cypress.
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