Siemens Accelerates Timing Closure for High Performance ASIC With Synopsys Physical Compiler

3/21/2003 - Synopsys, Inc. (Nasdaq:SNPS), the world leader in integrated circuit (IC) design software, announced that the Information and Communication Networks Division (ICN) of Siemens (NYSE:SI) used Synopsys Physical Compiler® to tape out the Switching Element SE9, a complex ASIC designed for extremely fast switching of asynchronous transfer mode (ATM) cells. The first application for the SE9 is in the mobile switching fabric of the ICM Division. Siemens ICN used Physical Compiler's unified synthesis and placement to generate a placed and optimized netlist. LSI Logic, a Siemens ASIC vendor, accepted this placed netlist and completed the design.

"We had a very tight time-to-market window on this difficult design, and could not afford to have multiple post-handoff iterations with our vendor," said Rudolf Krumenacker, vice president, Base Technology at Siemens, ICN. "Synopsys Physical Compiler's ability to drive timing closure helped us complete this aggressive design while achieving about 20 percent savings in design time." Siemens expected to have difficulty in meeting timing and achieving routability with the SE9, because of the large number of macros and multiple clock domains reaching about 200Mhz. Siemens decided to use the physical synthesis flow, which accelerates timing closure by accounting for physical effects earlier in the design cycle. All front-end activities, including placement, were done by Siemens ICN, using Design Compiler®, Physical Compiler, and PrimeTime®, all key components of the Synopsys GalaxyTM Design Platform. Back-end activities such as clock tree synthesis and routing were done at LSI Logic with Synopsys physical implementation tools, which are also part of the Synopsys Galaxy Design Platform.

"We support Physical Compiler in our FlexStream design system because it allows customers to take on more of the timing closure task, putting the iterative part of the design flow within the customers' control, resulting in more predictable schedules," said Ralf Leuchter, principal implementation support engineer, LSI Logic Corporation. "Accepting placement handoff from Physical Compiler enabled us to easily meet Siemens' schedule for the SE9."

"The timely and successful tapeout of the SE9 ATM switch is strong evidence of the benefits provided by the Galaxy Design Platform for advanced ASIC designs," said Jerry Lee, senior vice president & general manager, at Synopsys.

About Galaxy Design Platform
The Galaxy Design Platform is an open, integrated design implementation platform with best-in-class tools, enabling advanced IC design. Anchored by Synopsys' industry-leading IC implementation tools and the open MilkywayTM database, Galaxy Design Platform incorporates consistent timing, common libraries, delay calculation, and constraints from RTL all the way to silicon. The Galaxy Design Platform significantly reduces design time, decreases integration costs and minimizes the risks inherent in advanced, complex IC design.

About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is the world leader in electronic design automation (EDA) software for integrated circuit (IC) design. The company delivers technology-leading IC design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and is located in more than 60 offices throughout North America, Europe, Japan and Asia. Visit Synopsys online at

Synopsys, the Synopsys logo, Design Compiler, Physical Compiler and PrimeTime are registered trademarks of Synopsys, Inc. Galaxy and Milkyway are trademarks of Synopsys, Inc.

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