High-Speed DSP Simulation Time Drops from Months To Minutes

3/18/2003 - Xilinx, Inc., (NASDAQ:XLNX) announced its next generation System Generator for DSP tool v3.1 - the industry's most popular DSP software platform for FPGAs. New capabilities such as hardware-in-the-loop and HDL co-simulation enable designers of ultra high-speed DSP systems to significantly save development costs by cutting simulation time, in some cases from months to minutes. With the addition of hardware-in-the-loop, DSP designers now have access to a more familiar DSP design environment akin to conventional DSP processor design flows. For complete information about the new tool and the Xilinx XtremeDSP initiative, visit www.xilinx.com/dsp. The new tool will also be demonstrated at the upcoming Programmable World 2003.

"On the whole, we think the System Generator for DSP tool is better than any competing DSP design methodology. For our applications, the high-level schematic design flow, powerful MATLAB visualization, and proven IP cores are very effective," said Chris Musial, engineering manager at Boeing SVS. "We are now able to generate and refine algorithmic designs in a fraction of the time that it took to hand code VHDL. We really think this is a winner for Boeing, especially given its cost."

Increased Productivity and Reduced Design Costs
The new System Generator for DSP tool radically reduces simulation time and is the most cost efficient FPGA-based DSP design methodology available on the market today. The tool is designed to automatically translate DSP systems using The MathWork's MATLAB and Simulink tools into highly optimized VHDL and IP cores for Xilinx FPGAs. As a key component of the new tool, hardware-in-the-loop significantly accelerates the design cycle by allowing users to verify designs in hardware directly from the Simulink environment. With other DSP design methodologies, designers are required to verify designs in multiple design environments - a complicated process resulting in significantly slower simulation times. With hardware in the loop, DSP engineers can verify designs running in hardware in "real time" to make design decisions and changes earlier in the design process.

Internal benchmarks for designs running in "single step clock mode" (hardware in lockstep with software simulation) have resulted in performance improvements from 7X to 112X times faster than traditional simulation methods. When running hardware-in-the-loop using a free running clock, designers can now achieve up to six orders of magnitude improvement in simulation speed. This means that designers now have a simple way of simulating complex designs like BER testers that require many millions of samples that without hardware in-the loop, would take months to simulate. Hardware-in-the-loop is already supported by a number of development board vendors including AlphaData, Annapolis, Lyr, and Nallatech to provide designers with the choice to verify designs on their preferred hardware.

HDL co-simulation, another major component of the new tool, enables users to import legacy HDL code and provides hardware designers with system level modeling capability. The HDL co-simulation interface allows designers to reduce development costs and time by automatically invoking Mentor Graphics' ModelSim tool directly from Simulink and co-simulating HDL code together with Simulink models. Additionally, the new tool enables designers to model the DSP system control functions through MATLAB M-Code, Boolean expressions, and Xilinx's PicoBlaze soft microprocessor. These new features streamline the design process by incorporating data and control capabilities into a single environment.

"Our DSP customers are enthusiastically adopting the System Generator based flow to FPGAs because it makes key design tasks so easy to accomplish," said Ken Karnofsky, DSP/communications marketing director at The MathWorks. "The inclusion of hardware-in-the-loop and co-simulation in the new version will significantly increase customers' productivity and further accelerate the appeal of Xilinx's DSP solution."

Xilinx Virtex-II Series Solutions Underpin XtremeDSP Initiative
Today's announcement represents a major milestone in the Xilinx XtremeDSP initiative and further extends the company's leadership position in high performance DSP solutions. Xilinx's commitment to the importance of DSP technology resulted in the company's XtremeDSP initiative over two years ago.

Through its XtremeDSP initiative, Xilinx has already delivered a wide range of solutions:

Pricing and Availability
The new System Generator for DSP v3.1 is available now for use with Xilinx Virtex and Spartan Series FPGAs and is priced at $1995. For more information about the new System Generator for DSP tool and the XtremeDSP solution, visit www.xilinx.com/systemgenerator_dsp.

Programmable World 2003 Customers can learn more about the new System Generator for DSP tool and XtremeDSP initiative at Programmable World 2003 in San Jose on, May 6, Munich on May 15, Shanghai on June 16, Hsinchu on June 18, Seoul on June 20, and Tokyo on June 24. Customers will learn how to implement complex DSP applications such as Software Defined Radio using Xilinx Virtex-II Series FPGAs. The event will include in-depth technical DSP sessions from Xilinx. For complete program and registration information, visit www.xilinx.com/pw2003.

About Xilinx
Xilinx, Inc. (NASDAQ: XLNX) is the worldwide leader of programmable logic solutions. Additional information about Xilinx is available at www.xilinx.com.

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