3/17/2003 - Altera Corp. (NASDAQ: ALTR) will present "Design Guidelines for Optimal Results in FPGAs and ASIC Prototypes" at the Synopsys Users Group (SNUG) San Jose 2003 conference. The session will review FPGA design practices that result in improved timing performance, logic utilization, and system reliability. Design engineers will learn how to minimize problems when retargeting a design to different speed grades or device architectures.
The presentation is part of SNUG Session MD1 on "Methods for Improving Product Development."
When: Presentation: Monday, March 17 from 4:25 p.m. to 5:05 p.m.
SNUG San Jose: March 17-19, 2003
Where: Oak/Fir Room
San Jose Doubletree Hotel
2050 Gateway Place
San Jose, CA 95110
For additional information, visit: http://www.snug-universal.org/northamerica/na_sanjose.htm
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