3/5/2003 - Sequence Design unveiled its CoolTime technology, the foundation of an industry-first "instantaneous" voltage-drop analysis tool that will join the company's burgeoning portfolio of electrical-integrity analysis solutions for nanometer SoC design.
Power, voltage drop, timing, and signal integrity are interrelated and cannot be examined in isolation. CoolTime analyzes these electrical effects concurrently, and reduces runtimes over existing, fragmented solutions by up to 75 percent.
CoolTime is being demonstrated for the first time this week in the Sequence booth at Munich's DATE trade show. The technology will be available commercially in Q2, 2003.
"Companies at the leading-edge of design, noted experts such as the University of Michigan's Dr. Dennis Sylvester, and even Dr. Andy Grove, chairman of Intel, are evangelizing the importance of power integrity in the nanometer realm," said Vic Kulkarni, president and CEO of Sequence. "Within our NanoCool initiative, CoolTime provides an advanced analysis platform with a focus on power and signal-integrity issues. By addressing advanced physical effects, it ensures consistency of results and dramatically increases the probability of first-time silicon success for complex designs."
Instantaneous Approach For Dynamic Analysis
CoolTime overcomes inherent limitations in existing cell-based IR-drop tools. Rather than a static approximation of time-variant currents, CoolTime performs instantaneous current analysis to incorporate dynamic effects resulting from power-grid capacitance, package inductance, and on-chip decoupling capacitors. For designs under 130nm, these dynamic effects can contribute to as much as 30 percent to 50 percent of the total voltage drop. CoolTime examines both power and ground networks simultaneously to account for ground-bounce and power grid resonance.
High Performance and SoC Capacity
Benchmarks from beta customers provide convincing evidence of the tool's effectiveness. CoolTime's instantaneous mode runs at a rate of 2 million gates per hour, while static results scale to 25 million gates per hour and beyond. The embedded high-speed extractor is scalable and can process multimillion-net segments per hour.
"Design at 0.13u and below requires our design team to have a clear understanding of voltage drop and its impact on timing and signal integrity," said Jim Vanaria, director of COT Design Services at TranSwitch. "The Sequence CoolTime approach to instantaneous voltage drop analysis using STA techniques, is a unique solution that addresses a critical need in ensuring integrity of power grids. Integration with timing and signal-integrity analysis and optimization makes CoolTime an attractive solution."
"Instantaneous analysis is a requirement for accurately modeling inductive noise and decoupling capacitor effects," said Dr. Anantha Chandrakasan, professor of EECS at MIT. "Furthermore, delay effects cannot be modeled effectively using voltages computed from time-averaged currents . . . Anyway, this is cool!"
For the analysis of current, CoolTime has a patent-pending instantaneous vectorless algorithm, T2, that relies on timing constraints as user input. Unlike existing statistical approaches, it does not rely on probabilistic activity propagation methods, instead computing actual events on circuit nodes.
In addition, the tool supports simulation-based voltage-drop analysis, and can compute average IR drop for fast analysis during the pre-route phase to identify hot spots, structural weaknesses in the power grid, and via deficiencies.
Leverages Sequence Product Portfolio
While emphasizing its strengths in instantaneous voltage drop analysis, CoolTime simultaneously leverages production-proven Sequence technologies for power, parasitic extraction, timing, and signal-integrity analysis.
In addition to crosstalk-induced delay and glitch, CoolTime accounts for voltage-drop induced delays during timing analysis. CoolTime renders a complete timing and signal-integrity capability that accounts for on-chip and off-chip physical effects. With a built-in characterization engine for derating delays for voltage drop, CoolTime augments existing timing library formats for accurate timing analysis. An SDF output with voltage drop and crosstalk induced delays can be generated from CoolTime for signoff timing analysis.
CoolTime augments and complements the user's installed physical implementation flow for fast, full-chip signoff of hierarchical SoC designs by eliminating the need for multiple analysis tools and multiple iterations. CoolTime shares a common platform with Sequence's PhysicalStudio for pre- and post-route optimization of timing and signal integrity, thereby enabling fast and accurate design closure for nanometer SoC designs.
The production release of CoolTime will be available in Q2, 2003. For more information on evaluation licenses, contact email@example.com
Sequence Design, Inc., the SoC Design Closure CompanySM, enables system-on-chip designers to bring higher-performance and lower-power integrated circuits quickly to fabrication. Sequence's power and signal-integrity software give its more than 100 customers the competitive advantage they need to excel in aggressive technology markets, despite demanding complexity and time-to-market issues of nanometer design. Additional information is available at sequencedesign.com.
Sequence has worldwide development and field service operations. The company was recently named by Reed Electronics as one of the top 50 companies to watch in the electronics industry. Sequence is privately held. Sequence is a member of Cadence Design Systems' Connections and Mentor Graphics' Open Door partnership programs.
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