2/24/2003 - Consystant announced new enhancements to the StrataNP Design Suite, the company’s integrated development platform for the Intel® IXP2400 network processor. With StrataNP version 3.3, Consystant now offers line rate performance as well as a host of new highly integrated capabilities designed to accelerate the development of high performance, optimized code.
“The key problem facing developers of network processor applications is reducing their development time without sacrificing performance,” says Ross Ortega, President of Consystant. “With the new capabilities we've added to StrataNP, developers now have an extremely flexible and powerful tool that they can use to explore, optimize and validate their IXP2400 network processor software designs, minimize their costs and shorten the time-to-market of their products.”
Graphical Design Environment
To simplify software development for the IXP2400 network processor, StrataNP brings together a graphical design environment with a library of templates, example designs, reusable software components, and extensive design mapping, analysis and debugging capabilities. The environment integrates with the Intel® Internet Exchange Architecture Software Development Kit 3.0 toolkit allowing designers to rapidly combine a wide variety of proven data plane components from Intel and third parties to create applications for the IXP2400 network processor.
StrataNP is also compliant with the Intel® IXA Portability Framework, a modular programming architecture that accelerates development by maximizing code portability and reuse in network processor-based projects. This ensures that applications developed with StrataNP will comply with standard component design guidelines, and provide tight integration with the control plane API.
The latest version of StrataNP adds complete code synthesis at full line rate, allowing designers to validate their code at the highest performance levels. It also offers complete support for the IXP2400 network processor. Ever since StrataNP was first introduced, the design platform has offered developers unmatched ability to validate and optimize their design through its system analyzer. This highly productive tool gives developers the opportunity to visually track packet flow and trace events through each component across an entire application. The user can inspect packet data for each event, monitor hardware resource utilization, track overall packet rate, and trace latency across the entire system and within each component.
StrataNP 3.3 adds extensive debugging capabilities to the system analyzer that instantly link events in the packet flow to the corresponding microcode source file. “Now developers can not only see the packets flowing between components, they can click on events and bring up the actual source code,” notes Ortega. The latest release also allows developers to edit the microcode without leaving the design environment.
A number of additional enhancements help simplify code development and minimize design time. For example, intelligent mapping capabilities embedded in StrataNP help guide developers through critical stages of the design. This mapping capability allows developers to group software components into pipelines and allocate the pipelines to microengines and threads. In StrataNP 3.3 developers can also configure individual components as well as allocate the unique resources of the IXP2400 network processor such as next neighbor registers, scratch rings, queue arrays, SRAM channels, and DRAM. The design environment automatically generates the code needed to meet the developer's mapping choices, giving the developer more time to explore design options to maximize performance.
In addition, while StrataNP allows developers to rapidly build applications using microblock components in an intuitive graphical design environment, the platform has until now required designers to input those microblocks manually. StrataNP 3.3 simplifies that task by adding form-based input for microblocks.
Moreover, the upgraded environment features three newly wrapped microblocks for popular MPLS and IPv6 applications. These include an ILM Forwarder, a FTN Forwarder and an IPv6 Forwarder.
Pricing and Availability
StrataNP 3.3 for the Intel IXP2400 is available immediately. For more information including pricing and evaluation copies please contact Consystant.
About the Company
Consystant, a privately held company, provides an advanced software design environment for network processors. With Consystant's products, network equipment manufacturers can rapidly explore, design and develop network processor software achieving faster market delivery at lower development costs. Consystant's open environment leverages the best in complementary design solutions and maximizes software investment through reusable software components. Headquartered in Kirkland, Washington, Consystant is backed by Intel Capital Group, Lucent Venture Partners, and Singapore EDB.
Consystant is a member of the Intel(R) Communications Alliance, for more information please visit http://intel.com/go/ica Intel, IXP and XScale family are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
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