Pentek Introduced Five Highly-optimized GateFlow IP Core Libraries

2/19/2003 - Digital signal processing (DSP) design engineers are constantly looking for ways to boost embedded system performance levels by taking advantage of new technology. The use of Library IP (intellectual property) in conjunction with the high-performance DSP capabilities of Xilinx® Virtex®- Series FPGAs (Field Programmable Gate Arrays), can significantly offload computationally-intensive functions from the processor, thus reducing both system complexity and time to market.

Pentek, Inc. introduced five highly-optimized GateFlow IP Core Libraries that are the fastest in their class from any vendor. The Model 4954 GateFlow IP Cores are set apart by their speed, accuracy and performance, yielding tangible savings in system costs and development time. By encapsulating numerous man-months of optimization, enhancement, testing and documentation, each core offers a highly-reliable, fully-characterized, off-the-shelf computational engine all ready for deployment in high-performance, FPGA-based systems.

Pentek’s high-speed, wideband, digital-down converter IP cores outperform industry standard ASICs and now allow design engineers to take advantage of the latest class of wideband, monolithic A/D converters. The new FFT (Fast Fourier Transform) cores deliver an incredible tenfold speed advantage over the fastest programmable DSPs found in embedded systems. These IP Cores are ideal for radar, wireless and signal intelligence applications where speed and accuracy requirements dominate.

"The combination of our VirtexSeries FPGAs with the Pentek IP Core Library affords designers an innovative solution that reduces design cycles and optimizes system performance, for benefits in both the development and deployment phases of new projects,” said Jerry Banks, director of global alliances at Xilinx.

Pentek's GateFlow IP cores are engineered for Xilinx Virtex-II and Virtex-II Pro-compatible FPGA platforms and are highly integrated into Xilinx ISE design tool suite. As of now, the GateFlow IP Core Library consists of the following five functions:

"Pentek’s GateFlow IP Core Library is our latest commitment to help customers benefit from Xilinx’s industry-leading FPGA devices. It’s easy for customers to ‘test drive’ these new cores by downloading evaluation cores from our web site. With simulation tools, they can verify how these cores will perform in their final system, including resource utilization, operational characteristics and signal quality," said Rodger Hosking, vice president of Pentek, Inc. “Now system engineers can easily insert these world-class core functions into their designs to replace older technology, reduce the processor count, save costs, and boost performance –– all at the same time!"

Parallel FFT Engines Handle Four Data Streams Simultaneously
The GateFlow IP FFT Core 401 and the GateFlow IP FFT Core 404 are ultra-high-speed, pipelined 1024- and 4096-point complex FFT engines, respectively. Both FFT Cores fully exploit the numerous FPGA hardware multipliers to handle four parallel input and output streams. They are optimized for demanding real-time applications that require real-time sustained FFT calculations at aggregate input data rates up to 560 MSPS.

Calculation times for each FFT are 1.83 usec and 7.31 usec, for the 1024- and 4096-point cores, respectively. These execution speeds are over ten times faster than optimized FFT algorithms running on 500 MHz G4 PowerPCs or C6000 TI DSPs, delivering a tremendous performance advantage compared to computing FFTs on programmable processors.

The GateFlow FFT IP Core 403 is a fast, single pipelined 4096-point complex FFT optimized for real-time, sustained FFT calculations with input data samples rates up to 140 MSPS. Execution timing for this 4096 core is 29.26 usec. All three FFT cores provide an optional input Hanning window, complex I and Q outputs or optional output power (I2 + Q2) calculation, all available with zero data loss at the full clock rate.

GateFlow Digital Receiver IP Boost I/O Data Rates With Better Resolution
The GateFlow Wideband Digital Receiver IP Core 421 is a high-speed wideband digital down converter modeled after the Texas Instruments GC1012B, but with enhanced speed, performance and programmability. The Core 421 Digital Receiver increases input resolution from 12 bits to 16 bits for better accuracy and dynamic range. Handling both real and complex inputs with input data rates up to 140 MSPS, the 63 MHz maximum output bandwidth of the Core 421 receiver exceeds the GC1012B by 40%.

For extremely wide bandwidths, the GateFlow Wideband Digital Receiver IP Core 422 utilizes a proprietary dual processing architecture to handle real or complex input data samples up to 280 MSPS and deliver output bandwidths of up to 125 MHz.

Unlike the fixed filters of the GC1012B, both GateFlow receiver cores feature four sets of 18-bit user-programmable FIR filter coefficients for each of the six decimation factors of 2, 4, 8, 16, 32 and 64. With up to 1792 FIR filter taps, the FIR filter delivers superior stopband image rejection of more than 100 dB and excellent passband flatness of only 0.04 dB. Coupled with an extremely low distortion local oscillator, this greatly-improved signal processing path assures better signal-to-noise performance for optimal recovery of weaker signals.

Free Evaluation of Pentek’s GateFlow IP Cores
Engineers can download an evaluation copy of the GateFlow IP Core Library using ModelSim to test and simulate the functionality, speed and FPGA resource utilization and allocation of these cores. Engineers get a true representation of how these cores will behave within their own designs.

Other GateFlow Products
Pentek’s GateFlow product line also includes the GateFlow FPGA Design Kit for custom algorithm development and GateFlow Installed Cores featuring Pentek's streamlined FFT (Fast Fourier Transform) and Wideband Digital Receiver algorithms. Both of these GateFlow products are available for Pentek’s FPGA-board-level products.

For the latest pricing and availability information, please contact Mario Schiavone by phone at (201) 818-5900 ext. 229, or by email to

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