TI's New Customizable UMTS Infrastructure Chipset Slashes OEM ASIC Development Costs While Cutting Per-Channel Costs by 50 Percent

2/4/2003 - In a move that fundamentally changes 3G channel card design, Texas Instruments Incorporated (TI) (NYSE: TXN) introduced a programmable chipset that enables cellular infrastructure manufacturers to create low-cost, differentiated channel cards for 3G base stations without the burden associated with developing their own custom application specific integrated circuits (ASIC). The new chipset features a digital signal processor (DSP) tailored for wireless infrastructure and tightly coupled transmit and receive chip-rate application specific standard products (ASSP). This efficient and customizable combination will speed manufacturers to market with per-channel cost reductions of up to 50 percent.

For manufacturers, the new programmable UMTS digital baseband chipset offers a single platform that maintains the same flexibility as the popular DSP-plus-custom-ASIC solution but at a substantially lower cost. The cost savings come in two forms: first, manufacturers don't incur the development expense of creating their own custom ASIC - typically millions of dollars; and, second, they get a substantial savings on bill of materials (BOM) cost because the TI solution actually doubles channel density to 64 channels.

Of equal importance to cellular infrastructure manufacturers is the fact that the cost savings are delivered without sacrificing the ability to customize and differentiate their solution. In TI's chipset, the receive and transmit chip-rate ASSPs consist of flexible hardware configured via registers and commands under DSP software control, making differentiation not only possible, but simple.

"The new UMTS chipset from TI gives 3G wireless infrastructure OEMs what they want: improved cost and flexibility through the combined attributes of a DSP and a customizable ASIC," said Dr. Jim Gunn, wireless infrastructure analyst for Forward Concepts. "TI's innovative solution will help base station manufacturers drive down the cost of their equipment while giving them the flexibility to incorporate their algorithms and system intellectual property (IP)."

"Current WCDMA base station designs are still not economic enough for mass deployment in the market," said Sean Lavey, an analyst from IDC. "The need for flexibility in this evolving standard has made costly FPGAs the choice of most designs shipped over the past year, but we are now finding OEMs shifting most if not all of their baseband architectures to most cost-effective ASIC/ASSP approaches."

Chipset Features High-Performance DSP and Tightly Coupled ASSPs
The chipset includes the TMS320TCI100 DSP, the TMS320TCI110 receive chip rate coprocessor and the TMS320TCI120 transmit chip rate coprocessor. Together, they deliver all the benefits of a customizable ASIC and a DSP without the cost and time to market disadvantages associated with custom ASIC developments.

The TCI100 DSP is pin and code compatible with the popular TMS3206416 DSP. Like the 6416 DSP, the TCI100 DSP features two high-bandwidth parallel interfaces and Viterbi and Turbo embedded coprocessors.

The TCI110 is a customizable receive chip rate ASSP. With it, designers have a single device for finger de-spreading and random access channel (RACH) preamble detection and searching for 64 users. This is a 2x improvement over solutions available today, which support an average of 32 users. The TCI110 communicates with the TCI100 DSP via a 64-bit memory interface bus that operates at a clock rate of 122.88 MHz, giving the interface itself a bandwidth of 7.8 Gbps.

The TCI120 ASSP is highly flexible and supports a configurable number of sectors and users per sector. It features multiple spreading, scrambling and channel gain blocks, allowing any dedicated channel to be dynamically allocated across any sector. The TCI120 includes a multi channel buffered serial port (McBSP) interface for low-latency transfer of closed-loop data such as power control, closed-loop transmit diversity and acquisition indicator channel (AICH) information. TCI120 supports the newly standardized high-speed downlink packet access UMTS channel, known as HSDPA, with appropriate modulation and slot format options.

The new chipset also is designed to work with TI's recently announced GC5016 digital up/downconverter, the industry's first integrated four-channel wideband digital downconverter and upconverter that is ideal for radios in 3G wireless base transceiver systems.

Software and Development Tools Make The Chipset Easy To Use
The 3G product offering is augmented by development tools, foundation software and modular UMTS chip rate and symbol rate application libraries all geared to make the chipset easier to use and speed time to market. The tools include an evaluation module (EVM), which enables customers to begin early code development, and Code Composer Studio plug-in emulator probes that provide real-time diagnostic visibility into both the TCI110 and TCI120.

TI is committed to the cellular infrastructure market and offers manufacturers a broad product portfolio that includes tailored DSPs, ASSPs, high-performance analog solutions and power management devices.

Chipset Availability
The TCI100 DSP, the TCI110 and the TCI120 are scheduled to be available through TI in the third quarter of 2003. Download a white paper and UMTS chipset product bulletin today at www.ti.com/tci1xwp_wi.

Limited preliminary samples of the GC5016 wideband digital downconverter and upconverter are available today from TI. Production devices will be widely available in the third quarter of 2003. Download the GC5016 data sheet today at (www.ti.com/GC5016ds_wi).

Previous Page | News by Category | News Search

If you found this page useful, bookmark and share it on: