NEC Tapes Out 10 Million+ Gates Networking Chip with Magma Software

2/4/2003 - Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design solutions, and NEC Electronics America, Inc., announced that NEC Electronics America used Magma software to successfully tape out and achieve first-pass silicon success on a networking chip with more than 10 million gates and a maximum on-chip clock speed of 333 megahertz (MHz). The chip is packaged in a flip-chip package with peripheral as well as area input/outputs (I/Os). The chip was implemented hierarchically using NEC Electronics' CB-12 ASIC technology (0.15-micron technology node) with Magma's Blast PlanTM and Blast FusionTM design software systems.

The combination of Magma's advanced software and NEC Electronics' ASIC technology provided impressive improvements in turnaround time and congestion handling between the preliminary design and the final design. The hierarchical design capability in Blast Plan, including GlassBoxTM modeling, enabled full-chip analysis, top-level optimization and placement of area I/Os to support this nearly 2000-pin flip-chip design. In addition, Blast Fusion was able to reduce the cell count and cell area, thereby reducing the net count and minimizing congestion.

"This design had very high net count, which made managing congestion and timing very difficult," said Akira Denda, senior engineering manager, broadband LSI technology strategic business unit, NEC Electronics America, Inc. "With Blast Fusion's physical optimization capabilities, we were able to significantly reduce the cell count and cell area to maintain the initial die size. Our design also contained I/O slots in both the core and peripheral regions, flip-chip technology, 35 blocks and more than 400 memory macros. Magma's GlassBox data reduction technology and integrated planning and implementation system provided the accuracy and capacity we needed to meet the aggressive performance goals while maintaining the original die size."

"As a leading designer and manufacturer of innovative semiconductors, NEC Electronics America is known for using cutting-edge design tools and methodologies," said Rajeev Madhavan, chairman and CEO of Magma Design Automation. "We're very pleased that they include Magma software in their flow and share our commitment to providing mutual customers with solutions that meet their cost, performance and time-to-market requirements."

Powerful Optimizations and Unified Architecture Minimize Chip Area and Turnaround Time
Achieving timing closure and handling congestion on earlier generations of the design had required multiple, time-consuming iterations. Using Blast Fusion and Blast Plan, NEC Electronics America was able to achieve timing closure without returning to synthesis. Magma's systems are based on a single, unified data model architecture that contains all the logical and physical information about the design and is resident in core memory during execution. The various functional elements - such as the implementation engines for optimization, placement and routing, and the analysis software for timing and delay extraction - all operate directly on the single data model without relying on file interfaces or application program interfaces (APIs). This tight integration allows more accurate analysis of the design, and enables the system to make rapid tradeoff decisions during the design process to optimize for better chip performance and area.

Magma's systems are based on its patented FixedTimingTM methodology. This approach enables Magma's systems to predict circuit speeds prior to detailed physical design. The systems then use a series of design refinements during physical design to achieve a final timing that is very close to the predicted circuit speed. With predictable timing results, iterations from place and route back to synthesis can be eliminated and time to market can be significantly improved. FixedTiming also ensures that each cell is sized according to the actual wireload, resulting in lower cell counts and more compact layouts.

Magma Hierarchical Design Flow Eliminates Capacity vs. Accuracy Tradeoff
Blast Plan's hierarchical design capabilities and GlassBox technology were key to the successful completion of this design. Blast Plan uses the GlassBox abstraction technique to create models that contain the logical and physical information needed to generate accurate time budgets for the top-level blocks. The partitioning, pin placement and time-budgeting steps are performed with accurate data that is maintained in Magma's unified data model throughout the design process. In this way, the Magma flow delivers the capacity of a hierarchical design flow with the accuracy of a flat design approach.

About NEC Electronics America, Inc.
NEC Electronics America, Inc., headquartered in Santa Clara, Calif., is a wholly owned subsidiary of NEC Electronics Corporation, a leading provider of semiconductor products encompassing advanced technology solutions for the broadband and communications markets; system solutions for the mobile, PC, automotive and digital consumer markets; and platform solutions for a wide range of customer applications. NEC Electronics America offers solutions ranging from standard products to system-on-a-chip (SoC) solutions, customized products for next-generation designs, a local manufacturing facility in Roseville, Calif., and the global manufacturing capabilities of its parent company. NEC Electronics America also is the exclusive sales supplier of NEC active-matrix LCD and PDP modules in North America. More information about the products offered by NEC Electronics America, Inc. can be found at

About Magma Design Automation
Magma software is used to design fast, multimillion-gate integrated circuits, providing "The Fastest Path from RTL to Silicon"TM to enable chip designers to reduce the time required to produce complex ICs. Magma's products for prototyping, synthesis, and place & route provide a single executable for RTL-to-GDSII chip design. The company's Blast FusionTM, Blast Fusion APXTM, Blast PlanTM, Blast Noise® and Blast RTLTM products utilize Magma's patented FixedTiming® methodology and single data model architecture to reduce the timing-closure iterations often required between the logic and physical processes in conventional IC design flows.

Magma maintains headquarters in Cupertino, Calif., as well as facilities in Silicon Valley, Los Angeles, Orange County and San Diego, Calif.; Boston, Mass.; Durham, N.C.; Laurys Station, Pa.; Austin and Dallas, Texas; Newcastle, Wash.; and in Canada, China, France, Germany, India, Israel, Japan, Korea, the Netherlands, Taiwan and the United Kingdom. The company's stock trades on Nasdaq under the ticker symbol LAVA. Visit Magma Design Automation on the Web at

Magma, Blast Noise and FixedTiming are registered trademarks, and Blast Fusion, Blast Fusion APX, Blast Plan and "The Fastest Path from RTL to Silicon" are trademarks of Magma Design Automation. NEC Electronics America, Inc., is either a registered trademark or trademark of NEC Electronics Corporation in the United States and/or other countries.

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