0-In Design Automation Rolls Out Assertion-Based Verification Suite 2.1

12/16/2003 - 0-In Design Automation, the Assertion-Based Verification Company, announced that it has released Version 2.1 of its Assertion-Based Verification (ABV) Suite. This release supports the use of formal verification in integrated static flows prior to simulation, complementing 0-In's industry-leading dynamic ABV flows. V2.1 also contains important enhancements, including additional assertion checkers, two new protocol monitors, support for numerous RTL constructs from the Verilog-2001 standard, and support for assertion constructs from SystemVerilog and the Property Specification Language (PSL). All features in the 0-In ABV Suite V2.1 are in direct response to feedback from 0-In's customer base, which encompasses more than 14,000 assertion simulation licenses and over 2,000 formal verification licenses.

"Although all our customers using formal verification also use simulation, there are times in a project when simulation may be unavailable," said 0-In chairman and CTO Dr. L. Curtis Widdoes. "For example, a designer may want to run analysis on a block even before the verification team has set up the simulation environment. The integrated static capabilities in V2.1 allow the designer to get started with verification early in the process, running both automatic design checks and formal verification."

The Integrated Static Verification Process
The 0-In integrated static flow involves two tools in the 0-In ABV Suite - 0-In Checklist and 0-In Confirm. 0-In Checklist performs a wide range of automatic RTL design checks without the need to run simulation. These checks include identification of combinational feedback loops, detection of tri-state bus contention, and verification of signals crossing between asynchronous clock domains. Designers can run analysis during the earliest stages of development and re-run every time the design changes. Since 0-In Checklist has the power to analyze an entire chip quickly, it can also be run by the verification team periodically during development and just prior to RTL sign-off to ensure that all problems have been resolved.

0-In Checklist can generate assertions from several types of automatic checks for more extensive analysis by the 0-In Confirm static formal verification tool. The designer can specify additional assertions using the checkers in the 0-In CheckerWare library. 0-In Confirm performs deep, exhaustive analysis on both automatic and designer-specified assertions, reporting assertions that have been formally proven correct and counterexamples when exceptions are found. Counterexamples represent RTL errors that the designer must fix. 0-In Confirm has a much greater capacity than traditional model checkers, so the designer can run it on an entire chip sub-section and not just on individual blocks.

Since formal analysis from 0-In need not necessarily start from reset, 0-In Confirm can capture any legal design state from simulation for use as a starting point. In V2.1, 0-In Confirm adds the capability for determining the reset state even if no simulation is available. Once simulation is available, the complementary dynamic flows allow both the automatic assertions from 0-In Checklist and the designer-specified assertions to be run in any existing simulations as well as in the 0-In Search dynamic formal verification tool.

Enhancements to Assertion Library
The 0-In ABV Suite V2.1 includes significant enhancements to 0-In's CheckerWare library of assertion checkers and to its family of industry-standard protocol monitors. Three new checkers - always, never, and mutex - enhance ease of use for engineers familiar with traditional formal verification languages. Two new CheckerWare monitor products - Serial Attached SCSI and PCI-X 2.0 -- are now available. (See today's release entitled "0-In Verification IP Portfolio Grows to Include More than 25 CheckerWare Monitors" for product details.) In addition, V2.1 provides significant new functionality for ten existing checkers and three existing monitors.

"Our customers recognize the tremendous amount of IP and value embodied in our CheckerWare offerings," said 0-In president and CEO Steve White. "Our extensive customer base helps us keep pace with the constant advances in assertion specification and standard protocols, and ensures that we evolve our products in direct response to their needs."

Support for Evolving Language Standards
The 0-In ABV Suite V2.1 release adds support for numerous RTL constructs from the Verilog-2001 standard (IEEE 1364-2001), which is being used widely for design and verification. In addition, the release adds initial support for assertion features of the SystemVerilog and PSL standards from the language standards body Accellera.

"This is a period of rapid evolution for design, assertion and verification languages," noted Mr. White. "As the industry leader in ABV, 0-In is moving quickly to add support for the constructs that our customers are using or plan to use in the near future. We will continue to evolve our products as the standards develop and mature, supporting additional SystemVerilog and PSL constructs in our next release early in 2004."

V2.1 of the 0-In ABV Suite is immediately available by FTP or on CD-ROM. The 0-In ABV Suite V2.1 is available for Sun SPARC systems running Solaris 2.7, 2.8, 2.9 and compatible OS versions; Sun SPARC 64-bit systems running Solaris 2.8, 2.9 and compatible OS versions; HP systems running HP-UX 11.0 and compatible OS versions; and Linux systems running RedHat 7.1, 7.2, 7.3 and compatible OS versions.

About 0-In
0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV) solution built on industry standards that provides value throughout the design and verification cycle - from the block level to the chip and system levels. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.

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