11/5/2003 - Celoxica, Ltd. and Aldec, Inc. announced the availability of Active-HDL+C, an integrated FPGA design environment that combines Aldec’s Active-HDL design entry and mixed-HDL simulation technology with Celoxica’s DK engine for C-synthesis and co-simulation.
Extending Aldec’s recently announced support for Celoxica’s C-synthesis tool (see release: 21 May 2003, www.aldec.com/press/releases/?ID=221&year=2003), the combined Active-HDL+C package offers FPGA designers the productivity gains of mixing HDL with Handel-C from one integrated environment. The designer is not required to learn multiple design entry and verification tools; therefore, design creation, project management, documentation, HDL simulation, co-simulation (HDL and C), C-synthesis as well as interfaces to third party FPGA place and route tools are controlled within a single flow.
“This partnership with Celoxica is a natural extension of our goal to provide increased productivity to FPGA designers,” said David Rinehart, director of marketing at Aldec. “Combining the powerful elements of Celoxica’s Handel-C language with Active-HDL will allow users to implement functional specifications at the algorithmic level and then synthesize directly to the FPGA.”
“The size and complexity of today’s FPGAs demand the higher-levels of abstraction of C-based design,” said Jeff Jussel, vice president of marketing at Celoxica. “This joint package ensures that designers can take advantage of those higher-levels of abstraction in a way that fits seamlessly with their existing RTL IP and design flows.”
Active-HDL+C provides a comprehensive FPGA design environment that supports both traditional RTL as well as emerging C-based flows. The package provides block-based design entry for VHDL, Verilog and Handel-C, and then performs co-simulation of these blocks on a single screen from within Aldec’s mixed-language environment. By integrating Celoxica’s C-synthesis and co-simulation technology with Active-HDL, users can simulate C with HDL and compile software algorithms directly into device-optimised FPGA hardware, giving FPGA designers access to the latest devices from Actel, Altera and Xilinx. The package completes the design flow with timing simulation (EDIF Netlist or HDL netlist with SDF).
Pricing and Availability
The Active-HDL+C package is now available through both Aldec and Celoxica sales channels worldwide. Introductory pricing will be available through the fourth quarter of this year for the US and UK. Pricing begins at $35,000 for a single seat perpetual license of the complete Active-HDL (PE) dual language (mixed VHDL, Verilog and EDIF) and Celoxica DK (C-Synthesis and Co-Simulation) FPGA design environment.
An innovator in system-level electronic design automation (EDA), Celoxica is the technology leader in Software-Compiled System Design, a process that accelerates design productivity by using higher-level languages to directly drive design verification and implementation of hardware and software through a platform-based design methodology. By providing a proven route to hardware design using software techniques, Celoxica’s solutions redefine hardware and software partitioning to enable the use of reprogrammable logic devices in the development of electronics and reconfigurable systems.
Aldec, Inc., a 19-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs with its offices located around the globe. Continuous innovation, superior product quality and total commitment to customer service comprise the foundation of Aldec’s strategic objectives. Additional information about Aldec is available at: www.aldec.com.
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