Magma's RTL-To-GDSII System Enables Broadcom's 15-Million-Gate Design

10/20/2003 - Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design solutions, announced that Broadcom® Corporation (Nasdaq: BRCM), the leading provider of silicon solutions enabling broadband communications, has taped out a 15-million-gate design using Blast RTLTM and Blast Fusion®. Magma's integrated RTL-to-GDSII system was used to synthesize the largest and most complex block of the design. Using just a single Blast RTL license, performance goals were met and significantly faster total turnaround time was achieved. Blast Fusion was used to implement the entire design.

"Magma synthesis not only enabled us to achieve timing closure on the most complex block, its Early Silicon Performance timing and gain reports allowed us to identify and correct critical problems early," said Cheng-Feng Chang, engineering manager of Enterprise Switching at Broadcom. "Magma's high-capacity synthesis and fast runtime coupled with Blast Fusion's correct-by-construction physical implementation flow allowed us to accelerate the design effort with great quality and best returns on our EDA tools investments, significantly reducing our product development cycle time."

"Traditional design flows are inadequate for the new generation of ASICs and SoCs. Higher capacity, early performance predictability, faster time to market and lower costs are the key requirements for leading IC providers such as Broadcom," said Yatin Trivedi, director of product marketing at Magma. "We're pleased that Broadcom design teams worldwide continue to select Magma solutions for their advanced deep submicron design challenges."

Blast RTL and Blast Fusion: Integrating High-Capacity Synthesis and Advanced Place-and-Route Capabilities
Blast Create and Blast Fusion are key components of Magma's integrated RTL-to-GDSII system. This system is based on the patented FixedTimingTM methodology. This approach to synthesis and place-and-route enables Magma's system to predict circuit performance prior to detailed physical design. The system then uses a series of design refinements during physical design to achieve a final timing that is very close to the predicted performance. With predictable timing results, iterations can be eliminated, time to market can be significantly improved and a streamlined ASIC design hand-off can be achieved.

Unlike conventional flows, the Magma system uses gain-based synthesis. This approach provides an order of magnitude improvement in capacity and run time over conventional logic synthesis systems. Gain-based synthesis also ensures that each cell is sized according to the actual wire load, resulting in a circuit structure that is electrically well balanced and a layout that is more compact and uses less power than a layout derived using conventional approaches.

In addition to providing advanced synthesis and place-and-route technology, Magma's system is based on the industry's only unified data model architecture. This architecture is a key enabler of Magma's FixedTiming methodology and gain-based synthesis, as well as the system's ability to deliver automated signal integrity avoidance, detection and correction. Magma's single data model contains all the logical and physical information about the design and is resident in core memory during execution. In conventional synthesis and place-and-route systems, each tool in the flow has its own unique data model. Data is shared among tools through cumbersome file-based interfaces or through the implementation of an API and common database. Neither of these approaches can provide the inter-tool data sharing and analysis performance that is required to support the FixedTiming approach. In Magma's system, the various functional elements such as the implementation engines for synthesis, placement and routing, and the analysis software for timing, delay extraction and signal integrity, all operate directly on the single data model without relying on file interfaces or APIs. This tight integration allows more accurate analysis of the design, and enables the system to make rapid tradeoff decisions during the design process to optimize for better chip performance, area and power.

Blast RTL, Blast Create and Blast Fusion utilize the same libraries and fully support Verilog, VHDL, SDC and .lib, allowing complete migration of existing designs and timing information and easy adoption.

ESP Enables a Predictable Design Flow
The FixedTiming methodology, gain-based synthesis and unified data model allow Magma system to provide a predictable design cycle. The system generates ESP (Early Silicon Performance) reports with which designers can determine the timing feasibility of their design and analyze the design topology to ensure the constraints can be met. ESP reports also enable an RTL designer to identify any missing constraints and false or multi-cycle paths, and get feedback about the overall feasibility of the architecture. The ESP report can identify problems early, before handing off the design to the back-end team or SOC vendor, facilitating less-time-consuming and less-expensive fixes.

About Magma Design Automation
Magma software is used to design fast, multimillion-gate integrated circuits, providing "The Fastest Path from RTL to Silicon"TM, enabling chip designers to reduce the time required to produce complex ICs. Magma's products for prototyping, synthesis, and place & route provide a single executable for RTL-to-GDSII chip design. The company's Blast CreateTM, Blast Fusion®, Blast Fusion APXTM, Blast PlanTM and Blast Noise® products utilize Magma's patented FixedTiming® methodology and single data model architecture to reduce the timing-closure iterations often required between the logic and physical processes in conventional IC design flows. Magma also provides the PALACETM and ArchEvaluatorTM advanced physical synthesis and architecture development tools for programmable logic devices (PLDs). The company's stock trades on Nasdaq under the ticker symbol LAVA. Visit Magma Design Automation on the Web at

Magma, Blast Fusion, Blast Noise and FixedTiming are registered trademarks, and ArchEvaluator, Blast Create, Blast Fusion APX, Blast Plan, Blast Rail, "The Fastest Path from RTL to Silicon", and PALACE are trademarks of Magma Design Automation. Broadcom is a trademark of Broadcom Corporation and/or its affiliates in the United States and certain other countries.

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