Infrant, NEC Tapes Out 3-Million-Gate ASIC with Magma RTL-to-GDSII

10/20/2003 - Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design solutions, announced that Infrant Technologies and NEC Electronics America have taped out a 250 MHz, 3-million-gate network storage device using Magma's integrated RTL-to-GDSII system. Infrant Technologies performed RTL synthesis with Blast CreateTM using a flat design methodology and then handed off the design to NEC Electronics America for physical implementation using Blast FusionTM. The design was fabricated in the CB-12M 0.15-micron process technology. With Magma's software, Infrant and NEC Electronics America were able to tape out the device with zero layout-to-synthesis iterations, completing the design in just three months.

"This was a complex network storage device that contained 40 macros in both Verilog and VHDL and it was the first design we'd done using NEC Electronics America and Magma," said Paul Tien, CEO at Infrant Technologies. "With its gain-based synthesis, Early Silicon Performance (ESP) reports and full support for both languages, Magma offered the predictability, high capacity, fast turnaround time and smooth handoff that were key to the success of this design."

"Magma's RTL-to-GDSII flow provides a very straightforward ASIC design handoff," said John Fallin, general manager, Design Solutions Center at NEC Electronics America. "All the design data, the floorplan and the constraints are provided in a single data file or Volcano, simplifying data migration and ensuring accurate communication of design intent and requirements between us and the ASIC designer. With the Infrant design, we were able to import the Volcano in a matter of minutes. And, with Magma's integrated environment and the one-pass implementation flow, we were able to implement the design faster and with fewer engineers."

"Infrant Technologies presented very challenging requirements. It had a large, complex design for which its designers needed to maximize the quality of results and minimize the design cycle," said Yatin Trivedi, director of product marketing at Magma. "We're pleased that Infrant was able to leverage the tight integration of Blast Create and Blast Fusion to meet its performance and time-to-market requirements and achieve a smooth ASIC design handoff."

Integrated Synthesis and Physical Design System Streamlines ASIC Handoff
Blast Create and Blast Fusion are key components of Magma's integrated RTL-to-GDSII system. This system is based on the patented FixedTimingTM methodology. This approach to synthesis and place-and-route enables Magma's system to predict circuit performance prior to detailed physical design. The system then uses a series of design refinements during physical design to achieve a final timing that is very close to the predicted performance. With predictable timing results, iterations can be eliminated, time to market can be significantly improved and a streamlined ASIC design hand-off can be achieved.

Unlike conventional flows, the Magma system uses gain-based synthesis. This approach provides an order of magnitude improvement in capacity and run time over conventional logic synthesis systems. Gain-based synthesis also ensures that each cell is sized according to the actual wire load, resulting in a circuit structure that is electrically well balanced and a layout that is more compact and uses less power than a layout derived using conventional approaches.

In addition to providing advanced synthesis and place-and-route technology, Magma's system is based on the industry's only unified data model architecture. This architecture is a key enabler of Magma's FixedTiming methodology and gain-based synthesis, as well as the system's ability to deliver automated signal integrity avoidance, detection and correction. Magma's single data model contains all the logical and physical information about the design and is resident in core memory during execution. In conventional synthesis and place-and-route systems, each tool in the flow has its own unique data model. Data is shared among tools through cumbersome file-based interfaces or through the implementation of an API and common database. Neither of these approaches can provide the inter-tool data sharing and analysis performance that is required to support the FixedTiming approach. In Magma's system, the various functional elements such as the implementation engines for synthesis, placement and routing, and the analysis software for timing, delay extraction and signal integrity, all operate directly on the single data model without relying on file interfaces or APIs. This tight integration allows more accurate analysis of the design, and enables the system to make rapid tradeoff decisions during the design process to optimize for better chip performance, area and power.

Blast RTL, Blast Create and Blast Fusion utilize the same libraries and fully support Verilog, VHDL, SDC and .lib, allowing complete migration of existing designs and timing information and easy adoption.

ESP Enables a Predictable Design Flow
The FixedTiming methodology, gain-based synthesis and unified data model allow Magma system to provide a predictable design cycle. The system generates ESP (Early Silicon Performance) reports with which designers can determine the timing feasibility of their design and analyze the design topology to ensure the constraints can be met. ESP reports also enable an RTL designer to identify any missing constraints and false or multi-cycle paths, and get feedback about the overall feasibility of the architecture. The ESP report can identify problems early, before handing off the design to the back-end team or SOC vendor, facilitating less-time-consuming and less-expensive fixes.

About Magma Design Automation
Magma software is used to design fast, multimillion-gate integrated circuits, providing "The Fastest Path from RTL to Silicon"TM, enabling chip designers to reduce the time required to produce complex ICs. Magma's products for prototyping, synthesis, and place & route provide a single executable for RTL-to-GDSII chip design. The company's Blast CreateTM, Blast Fusion®, Blast Fusion APXTM, Blast PlanTM and Blast Noise® products utilize Magma's patented FixedTiming® methodology and single data model architecture to reduce the timing-closure iterations often required between the logic and physical processes in conventional IC design flows. Magma also provides the PALACETM and ArchEvaluatorTM advanced physical synthesis and architecture development tools for programmable logic devices (PLDs). The company's stock trades on Nasdaq under the ticker symbol LAVA. Visit Magma Design Automation on the Web at

Magma, Blast Fusion, Blast Noise and FixedTiming are registered trademarks, and ArchEvaluator, Blast Create, Blast Fusion APX, Blast Plan, Blast Rail, "The Fastest Path from RTL to Silicon", and PALACE are trademarks of Magma Design Automation.

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