Magma Supports Actel's ProASIC Plus FPGAs with Physical Synthesis Tool

10/15/2003 - Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design solutions, announced that Magma's PALACE physical synthesis software now supports Actel's reprogrammable, flash-based ProASIC Plus field-programmable gate array (FPGA) device families. This support is the result of a 7-month-long, close collaboration between Actel and Aplus Design Technologies, Inc., which was acquired by Magma in July 2003. PALACE provides FPGA designers with significantly higher quality of results (QoR) and much faster timing closure. Extensive benchmarking shows that it provides an average of 20 percent better performance (Fmax) for ProASIC Plus designs than the best available synthesis flow, with a peak performance improvement exceeding 85 percent. Other benefits of the software include increased predictability, lower design costs and reduced design cycles.

"By working with Aplus and now Magma, we continue to ensure the availability of best-in-class EDA tools that support our ProASIC Plus family, the fastest ramping product in the company's history. We are excited to provide our customers with a solution that enables significant performance improvements and addresses the timing closure challenges that so many of them are facing today. The combination of technologies from both companies offers a compelling advantage to designers doing complex FPGAs or ASIC designers who want to leverage programmable logic in an ASIC design flow," said Saloni Howard-Sarin, tools marketing director at Actel.

"We've been working closely with Actel since the beginning of the year to bring the benefits of our unique push-button technology to their successful ProASIC Plus devices. With a unified timing model, advanced optimization, mapping and constraint-driven placement engines, the PALACE solution ensures better QoR while eliminating much of the manual intervention required in other solutions," said Behrooz Zahiri, director of marketing and business development for structured and programmable solutions at Magma. "With the acquisition of Aplus, Magma can continue to enhance and expand its structured and programmable solutions to provide complete, best-in-class physical synthesis tools for all major FPGA and structured ASIC platforms."

PALACE addresses the high-performance requirements of today's challenging FPGA designs. To produce the superior quality of results with minimal effort, PALACE unifies logic synthesis and physical design and provides an efficient physical synthesis engine for FPGAs that includes constraint-driven optimization, architecture-specific mapping, and unique support for multi-cycle on-chip communication. PALACE has consistently demonstrated at least one speed grade performance improvement over a wide range of FPGA architectures through push-button physical synthesis.

About the ProASIC Plus Family
The ProASIC Plus family, Actel's second-generation of flash-based FPGAs, consists of seven devices ranging in density from 75,000 to 1-million system gates. The combination of a fine-grained, single-chip ASIC-like architecture and nonvolatile flash configuration memory makes Actel's ProASIC Plus offering a strong ASIC alternative. The devices are live at power up, low power, highly secure and require no separate configuration memory, all characteristics shared by ASICs. Key features of the ProASIC Plus family include multiple phase-locked loops (PLLs), support for up to 198k bits of two-port embedded SRAM and 712 user-configurable I/Os, and improved in-system programmability (ISP).

About Magma Design Automation
Magma software is used to design fast, multimillion-gate integrated circuits, providing "The Fastest Path from RTL to Silicon"TM and enabling chip designers to reduce the time required to produce complex ICs. Magma's products for prototyping, synthesis, and place & route provide a single executable for RTL-to-GDSII chip design. The company's Blast CreateTM, Blast Fusion®, Blast Fusion APXTM, Blast PlanTM, Blast Noise®, Blast RailTM and Blast RTLTM products utilize Magma's patented FixedTiming® methodology and single data model architecture to reduce the timing-closure iterations often required between the logic and physical processes in conventional IC design flows. Magma also provides PALACETM and ArchEvaluatorTM advanced physical synthesis and architecture development tools for programmable logic devices (PLDs). The company's stock trades on Nasdaq under the ticker symbol LAVA. Visit Magma Design Automation on the Web at

Magma, Blast Fusion, Blast Noise and FixedTiming are registered trademarks, and ArchEvaluator, Blast Create, Blast Fusion APX, Blast Plan, Blast Rail, Blast RTL, "The Fastest Path from RTL to Silicon", and PALACE are trademarks of Magma Design Automation.

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