10/8/2003 - As part of its strategy to ensure unified standards for advanced design and verification, Cadence Design Systems, Inc. (NYSE: CDN) announced support for SystemVerilog. Cadence® is committed to accelerating the process of bringing SystemVerilog from a specification to a fully implemented international standard. The initial developer of the Verilog® language and a pioneer in the concept of open language standards, as exemplified by the creation of OVI in the early 1990s, Cadence provides current and continuing support for the VHDL, Verilog, PSL/OVL, SystemC, Verilog-AMS, and VHDL-AMS standards.
During the next weeks, Cadence will roll out plans for SystemVerilog support in its IncisiveTM verification and EncounterTM digital IC design platforms, as well as plans for smoothing the path of SystemVerilog through the Accellera and IEEE standards process. To drive this process, Cadence has named Victor Berman, an industry veteran in language standardization, to lead Cadence's language and standardization strategy.
"Victor has a strong track record in driving the opening of the Verilog language. With his talent, experience, and Cadence management support, he will ensure that this strategic move is successful," said Penny Herscher, Cadence executive vice president and general manager of the Design and Verification Group. "Victor's impact on the EDA industry has been extremely positive. His efforts have helped produce tremendous design team benefits and helped open up significant markets in simulation and HDL-based tool sales, which would never have happened if Verilog had remained closed and proprietary."
"Cadence supplies a very broad set of design tools and capabilities; my job is to ensure that the semantics of standards implemented at different levels and by different tools can be used together in a productive way," said Berman. "This is best achieved when standards are developed in a unified way with open input from all interested parties. I am looking to the IEEE to provide that unification in the evolution of Verilog."
"While Cadence understands the importance of the evolution of Verilog, it fully realizes that this is only a small piece of the design and verification puzzle," said Jay Lawrence, Cadence senior architect. "As a leader of open standards, Cadence has been active in many areas, such as the Accellera Property Specific Language (PSL), Open SystemC, VSIA SoC standards, and OpenAccess for efficient access to design data. While there are standards in many areas, the key to effective design and IP transfer is ensuring that these standards can be used to improve interoperability."
Berman has more than 20 years of experience championing standards issues in the EDA industry, which included the standardization of VHDL and serving as chairman on the IEEE Design Automation Standards Committee for six years.
To date, Cadence has donated and opened up more than a dozen major proprietary languages and formats to the industry, including Verilog, GDSII and SDF. The Incisive verification platform—the only platform in the industry that supports all broad languages on a single kernel—is working proof of Cadence's commitment to standards.
Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics based products. With approximately 5,000 employees and 2002 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.
Cadence, the Cadence logo, Virtuoso, and Verilog are registered trademarks, and Incisive and Palladium are trademarks of Cadence Design Systems, Inc. in the U.S. and other countries.
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