Chip-to-Chip Interconnect Specification 1.05 Released by HyperTransport Technology Consortium

1/30/2003 - The HyperTransport Consortium, a nonprofit industry organization that manages the HyperTransport technology specification, announced the formal release of 1.05 HyperTransport Technology I/O Link Specification. This new release defines several important new HyperTransport technology features, including a new HyperTransport switch function, enhanced PCI-X 2.0 interworking support, increased concurrency and 64-bit addressing. The new specification extends the set of electrical and protocol definitions and enables a new class of HyperTransport-based products.

“This new backward compatible specification paves the way for the HyperTransport industry to extend the capabilities of the technology without making existing products obsolete,” states Gabriele Sartori, President of the HyperTransport Technology Consortium. “HyperTransport-enabled systems can now be easily expanded with low-latency HyperTransport switches and enabled to link to popular PCI-X 2.0 devices. Once again the members of the Consortium have responded to the needs of the industry at large by improving the HyperTransport specification to include popular new features needed for advanced applications without affecting previous generations of product.”

The HyperTransport Technology Consortium Technical Working Group defined the HyperTransport Specification Release 1.05. States Brian Holden, Principal Engineer in PMC-Sierra's MIPS Processor Division and Chair of the Technical Working Group, “Over the past year we worked with our member companies to understand exactly what was needed to extend the existing specification to speed the development of networking and server applications. This new specification gives system designers added features that will be helpful in large HyperTransport-based server applications.”

The HyperTransport Specification Release 1.05 adds four major features to the existing HyperTransport technology specification: HyperTransport switches, enhanced PCI-X 2.0 interworking, greater transaction concurrency, and 64-bit addressing.

The HyperTransport switch function enables the connection of virtually unlimited numbers of HyperTransport devices. In addition, by switching traffic locally, the HyperTransport switch reduces latency and potential bandwidth logjams. The switch definition supports the concatenation of multiple width buses that in turn allows system designers to apply just the right amount of bandwidth in a particular section of a design. This in turn reduces overall system cost while maintaining maximum chip-to-chip I/O bandwidth. With logical partitioning and reset isolation, switch fabric fail-over is supported resulting in more robust systems. Logically, a switch appears to the system as a tree of PCI-compatible devices and bridges. A given switch can be partitioned to support several separate trees.

The HyperTransport Release 1.05 enhanced PCI-X 2.0 interworking features simplify the connection of HyperTransport-enabled systems to PCI-X 2.0 subsystems. Included are support for PCI-X 2.0 error indications and the ability to handle device configuration messages of up to 4K bytes. This supports the 128 byte burst message feature in PCI-X 2.0.

The HyperTransport Release 1.05 concurrency feature allows a system to have more than the previous 32 requests outstanding. This situation can occur in networking or server applications where a given data stream pipeline is “clogged” with outstanding requests that have not been fulfilled. This new feature eliminates this potential bottleneck in networking applications by allowing up to 128 outstanding requests.

The HyperTransport Release 1.05 64-bit addressing feature extends the original specification's 40-bit address in order to support large address spaces needed by some large networking and server applications. The 64-bit command feature is backward compatible with older address schemes, making the 64-bit address optional and enabled on a link-by-link basis.

About HyperTransportTM Technology
HyperTransport universal chip-to-chip interconnect technology replaces and improves upon existing multilevel buses used in systems such as personal computers, servers and embedded systems while maintaining software compatibility with PCI I/O technologies. HyperTransport technology delivers a maximum 12.8 GB/second aggregate bandwidth using easy to manufacture dual, unidirectional point-to-point links. Enhanced 1.2V low-power LVDS signaling and dual-data rate data transfers deliver increased data throughput while minimizing signal crosstalk and EMI. HyperTransport interconnect technology employs a packet-based data protocol to eliminate many sideband signals (control and command signals) and supports asymmetric, variable width data paths.

About the HyperTransportTM Technology Consortium
The HyperTransport Technology Consortium is a non-profit organization managed by its members that is dedicated to promoting HyperTransport technology as an open, freely available industry specification for high bandwidth chip-to-chip communications. Membership in the consortium is open to any industry participant for a modest administrative fee and includes the rights to royalty-free use of HyperTransport technology Intellectual Property. More information can be obtained from the HyperTransport Technology Consortium website at Advanced Micro Devices, Alliance Semiconductor, Apple Computer, Broadcom Corporation, Cisco Systems, NVIDIA, PMC-Sierra, Sun Microsystems, and Transmeta are promoter members and comprise the Executive Committee of the HyperTransport Technology Consortium.

Companies interested in HyperTransport technology are invited to join the consortium. Consortium members pay modest annual dues and receive a royalty-free license to use HyperTransport IP, gain access to additional technical documentation and may attend consortium meetings and events. To become a member, visit the consortium Web site at

HyperTransport is a trademark of the HyperTransport Technology Consortium.

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