Cypress Enhances Run-Time And Support of Popular Warp CPLD Development Tool

1/28/2003 - Cypress Semiconductor Corporation (NYSE: CY) launched the latest release of the Warp® design tool and environment. Now with enhanced performance, Warp Release 6.3 (Warp R6.3) tool includes timing constraints specification capability, faster run-time, improved project management, and expansion of support for Cypress’s industry-leading family of complex programmable logic devices (CPLDs). With over 28,000 software seats in place around the world and used in over 150 universities, the Warp development tool is one of the most popular HDL-based CPLD development tools in the world.

Powerful and easy-to-use at every step in the development process, Warp R6.3 supports all of Cypress’s programmable logic devices, including the Delta39KTM and Ultra37000TM CPLD families and the Programmable Serial Interface (PSITM) family of physical layer (PHY) devices. Warp R6.3 enables designers to develop programmable PHY solutions for next-generation communications systems in the InfiniBandTM, ESCON, Fibre Channel, Gigabit Ethernet, and SMPTE markets.

“With a comprehensive design, synthesis, and simulation environment, the latest Warp R6.3 development tool offers complete software support for CPLDs,” said Rajiv Nema, product marketing manager for CPLDs at Cypress. “Warp R6.3 provides the capabilities of tools costing much more, enabling designers to capitalize on the performance and speed-to-market advantages of programmable logic with a minimal software investment.”

WarpR6.3 Features
Warp R6.3 adds the ability to specify timing constraints for all of the Delta39K CPLDs and programmable PHY devices. Significant run-time improvements have been made to the Warp front end in all versions of the Warp development tool to speed up the design process. For Warp Professional and Enterprise versions, compilation time enhancements have been made to the design flow manager. Cypress has also added valuable features such as report file bookmarking to improve project management and expanded support for Delta39K family of CPLDs.

On the PC platform, Warp R6.3 includes the post-synthesis timing simulator Active-HDL SimTM version 3.3 and the finite-state machine (FSM) editor Active-HDL FSMTM, from Aldec Inc. Active-HDL Sim is a full-featured post-synthesis VHDL timing simulator that supports simulation of VHDL and Verilog files compiled to Cypress devices.

Pricing and Availability
Cypress continues to offer a value-driven $99 edition of Warp R6.3, along with two editions that provide additional design functionality: Warp Professional and Warp Enterprise. Cypress also offers industry-leading value by providing customers with free technical support and free upgrades for life. The Warp R6.3 update is free to existing Warp tool users and can be downloaded off the Cypress website today at

About Cypress
Cypress Semiconductor Corporation (NYSE: CY) is Connecting From Last Mile to First MileTM with high-performance solutions for personal, network access, enterprise, metro switch, and core communications-system applications. Cypress ConnectsTM using wireless, wireline, digital, and optical transmission standards, including Bluetooth, USB, Fibre Channel, SONET/SDH, Gigabit Ethernet, and DWDM. Leveraging its process and system-level expertise, Cypress makes industry-leading physical layer devices, framers, and network search engines, along with a broad portfolio of high-bandwidth memories, timing technology solutions, and programmable microcontrollers. More information about Cypress is accessible online at

Cypress, the Cypress logo and Warpare registered trademarks of Cypress Semiconductor Corporation. “Connectivity From Last Mile to First Mile,” “Cypress Connects,” Delta39K and Ultra37000are trademarks of Cypress.

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