Texas Instruments Delivers First Chip Made on Advanced 90nm Process

1/24/2003 - Texas Instruments Incorporated (TI) (NYSE: TXN) announced delivery of a fully-functional wireless digital baseband from its next generation, 90 nanometer (nm) process. The transition to 90nm offers many benefits to TI customers moving their designs to TI's most advanced manufacturing technology. By shrinking the dimension of the transistors' power consumption, size and manufacturing costs are reduced relative to the previous manufacturing process. Distances between transistors are also reduced, increasing overall processor performance and allowing integration of many more features on an equivalent size chip. TI is one of the first semiconductor companies to deliver working 90nm products.

"With the delivery of working 90nm products, TI has again demonstrated the benefit customers derive by working with a semiconductor company that owns its own technology roadmap and manufacturing," said Dr. Hans Stork, senior vice president and director of TI's silicon technology development. "Our R&D investment has led to the development of a set of very advanced CMOS processes that deliver the integration and circuit optimization required to match device architectures with the targeted application area."

TI's 90nm process features transistors as small as 37nm, a width 2000 times smaller than the thickness of newsprint. With the ability to pack over 400 million transistors on a single chip, TI's technology is driving cost-effective, system-on-a-chip (SoC) solutions with unprecedented levels of performance and power savings for TI products.

With up to nine layers of copper metal, TI's 90nm process also supports integration of a wide array of analog and radio frequency (RF) components for SoC development. Integration of analog and RF components for communication transmit and receive functions, and for analog-to-digital and digital-to-analog conversion circuits, is critical to a wide range of signal processing applications.

TI continues to offer extremely competitive embedded SRAM in the 90nm process, with densities up to 800 Kbits/mm2. In 2005 TI plans to also deliver its 90nm embedded FRAM technology; a low cost, high density, low-power, non-volatile memory alternative.

Optimized Process Flows
Previous process generations typically utilized a single pair of CMOS transistors optimized to support all the circuit functions on a chip. However, TI´s 90nm process makes it possible to use a collection of transistors that are "tuned" for different functions on a single chip to meet a variety of performance, density and power consumption requirements. This is done through adjustments to the transistors´ gate length, threshold voltage, gate oxide thickness or bias conditions. The result is that transistors with the highest performance can be used in performance critical functions such as signal processing, whereas transistors with lower power consumption can be used to support functions with lower active performance requirements to minimize system power. TI expects this capability to reduce system power by two to three times in future products while simultaneously increasing performance.

Flexibility to Meet Application Requirements
TI will offer several optimized 90nm process flows to meet the unique needs of a variety of end products and applications. The company´s first 90nm product was produced using the GS50 library that will allow for lower power operation, longer battery life and less heat generation. This process is optimized for devices such as 2.5 or 3G wireless phones, PDAs, digital cameras and Internet audio players. In addition to GS50, TI´s high performance ASIC and DSP products will run on SR50, a process flow that combines a balance of performance and power consumption. The third flow will be a high-performance computing products flow that Sun Microsystems will target for next generation UltraSPARC processor-based workstations and servers. Given the smaller geometries, the optimized transistors and metal interconnect system, TI estimates that UltraSPARC processor performance will double over today´s solutions. Devices will also achieve considerable power savings by migrating to 90nm technology, enabling higher density system designs for Sun products.

TI's 90nm process integrates a low-k dielectric, Organo-Silicate Glass (OSG) that has a k-value (dielectric constant) of 2.8. TI has extended its history as an innovator in gate dielectric materials, as this process is the 3rd generation of TI's technology to use a Plasma Nitrided Oxide (PNO) for the core transistors, which will be scaled to 1.2nm for the first time. PNO maintains the transistors' high level of reliability, minimizes gate leakage and allows TI's 90nm technology to meet its performance benchmarks.

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