9/30/2002 - The X Initiative, a semiconductor supply-chain consortium chartered with accelerating the availability and fabrication of the revolutionary X Architecture, announced that member companies Cadence Design Systems, DuPont Photomasks, and Numerical Technologies have successfully produced the first X Architecture photomask for the 130 nanometer semiconductor process technology node. This design-to-manufacturing collaboration tested each step of the lithography supply chain for photomasks supporting 130 nanometer design rules, and included optimization results for optical proximity correction (OPC). All phases of the mask production fell within the range of normal as compared to traditional designs. These results will help accelerate the adoption of the X Architecture as a production-worthy approach to the pervasive use of diagonal interconnect, which reduces total on-chip wiring by more than 20 percent and via-count by more than 30 percent, delivering simultaneous improvements in chip performance, power consumption and overall cost.
In the experiment, Numerical performed OPC using its iN-TandemTM OPC software on 130 nm X Architecture design data supplied by Cadence, and performed mask data preparation using Numerical's CATSTMsoftware. DuPont Photomasks created the mask using the ALTA® 4000 system from X Initiative member company Etec Systems, Inc., an Applied Materials, Inc., company. DuPont Photomasks then successfully inspected the reticles using KLA-Tencor's TeraStarTM system - the first time this system has been used to inspect X Architecture photomasks.
Previous photomask experiments at the 180 nanometer process node had highlighted OPC as an area for further investigation, as OPC is a requirement for most designs at 130 nanometers. Numerical utilized the unique customizable shape-based features of its iN-Tandem Hybrid OPC tool to optimize for the octagonal features of X Architecture designs. The OPC results were confirmed first through Numerical's silicon-accurate process simulation, as well as by the test mask successfully produced by DuPont Photomasks.
Jim Jordan, director of business development for DuPont Photomasks, said, "We believe that it's essential for the industry to increase cooperation to address design-to-manufacturing challenges and feel that the X Initiative is an excellent model of how to do it right. The production of masks supporting 130 nanometer X Architecture designs that utilize new OPC and reticle inspection solutions demonstrates what can be achieved through the combined talents of DuPont Photomasks and other leading-edge technology companies."
Aki Fujimura, corporate vice president and general manager of design for manufacturing at Cadence, noted that this work reflects significant progress against the X Architecture roadmap presented by the X Initiative in April. "It's impressive that market leaders such as DuPont Photomasks and Numerical have been able to demonstrate optimized results for the X Architecture at this advanced process node in such a short period of time. In parallel, Cadence Design Foundry has obtained test chip results to help Cadence Design Foundry design teams build and optimize their tapeout methodology for X Architecture designs."
More information about the X Initiative and the aforementioned mask results will be presented at the X Initiative Open Forum on Thursday, October 3, 2002, in rooms 203 and 204 of the Santa Clara Convention Center in Santa Clara, Calif., beginning at 12 noon, Pacific Time. Admission to the luncheon event is free of charge and open to all interested in attending. Speakers will include Chris Aquino, RAPID applications manager at KLA-Tencor, Michael Sanie, director of marketing and business development, IC design, at Numerical, and Aurangzeb Khan, corporate vice president and general manager of Cadence Design Foundry. At this event, the X Initiative will debut the Rygler Report, its new quarterly, state-of-the-industry report focusing on design-to-manufacturing challenges and solutions presented by industry veteran and advisor to the X Initiative, Ken Rygler.
"The X Initiative is building one of the best bridges we have today between silicon design and manufacturing. We need to foster more dialog and cooperation like this in the industry if we are to continue extend Moore's Law on the current two year cycle and grow the number of design starts at and beyond 90 nanometers. I look forward to increasing the intensity of this dialog through the sponsorship of the X Initiative," commented Rygler.
About the X Architecture
The X Architecture, the first production-worthy approach to the pervasive use of diagonal interconnect, reduces the total interconnect, or wiring, on a chip by more than 20 percent and via-counts by more than 30 percent, resulting in simultaneous improvements in chip performance, power and cost. For the past 20 years, chip design has been primarily based on the defacto industry standard "Manhattan" architecture, named for its right-angle interconnects resembling a city-street grid. The X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees from a Manhattan architecture. The new architecture maintains compatibility with existing cell libraries, memory cells, compilers and IP cores by preserving the Manhattan geometry of metal layers one through three.
About the X Initiative
The X Initiative, a group of leading companies from throughout the semiconductor industry, is chartered with accelerating the availability and fabrication of the X Architecture, a revolutionary interconnect architecture based on the pervasive use of diagonal routing. The X Initiative's five-year mission is to provide an independent source of education about the X Architecture, to facilitate support and fabrication of the X Architecture through the semiconductor industry supply chain, and to survey usage of the X Architecture to track its adoption. Representing leaders spanning the entire design-to-silicon infrastructure, X Initiative members include: Artisan Components, Inc.; ASML Netherlands B.V.; Cadence Design Systems, Inc.; Dai Nippon Printing (DNP); DuPont Photomasks, Inc.; Etec Systems, Inc., an Applied Materials, Inc. company; HPL Technologies, Inc.; Hoya Corporation; KLA-Tencor Corporation; Leica Microsystems AG; Matsushita Electric Industrial Co., Ltd.; MicroArk Co. Ltd.; Monterey Design Systems, Inc.; Numerical Technologies, Inc.; NurLogic Design, Inc.; PDF Solutions, Inc.; Photronics Inc.; Prolific Inc.; RUBICAD Corporation; Sagantec; Sanyo Electric Co., Ltd.; Silicon Logic Engineering, Inc.; SiliconMap, LLC.; Silicon Valley Research Inc.; STMicroelectronics; Sycon Design, Inc.; Tensilica, Inc.; Toppan Printing Co.; Toshiba Machine Co., Ltd.; Toshiba Corporation; Virage Logic, Inc.; Virtual Silicon Technology, Inc.; and Zygo Corporation. Membership is open to all companies throughout the semiconductor supply chain.
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