Xilinx Ships World's First PowerPC with RapidIO Interface

9/24/2002 - Xilinx announced the immediate availability of its Virtex-II ProTM device containing the world's first PowerPC processor with RapidIOTM interface. System architects in need of an overall system performance boost can now leverage the tightly integrated IBM PowerPC processor and RapidIO interface to implement high performance, low latency applications such as network control planes, DSP traffic aggregation and enterprise storage channel processing. Developed in collaboration with IBM, the complete solution leverages the embedded PowerPC processors and proven SelectI/OTM-Ultra of the Xilinx Virtex-II Pro programmable platform.

Today's news underscores the benefits of the technology relationship between Xilinx and IBM in bringing innovative and flexible new solutions to market. The Xilinx Virtex-II Pro FPGAs are the result of a collaborative design effort between the two companies to deliver a new platform for use in communications, storage, and consumer applications.

"We're working with Xilinx to provide our embedded PowerPC customers with new development options for their products," said Scottie Ginn, vice president of standard products for the IBM Microelectronics Division. "We believe Xilinx's integration of PowerPC, Virtex-II Pro, and RapidIO technologies represents a unique and powerful combination."

"Xilinx is pleased to be collaborating with our key partner IBM to accelerate the industry-wide adoption of the RapidIO interface," said Rich Sevcik, senior vice president of FPGA Products at Xilinx. "Starting with our introduction of the first RapidIO core in May, 2001, Xilinx continues to offer the industry's broadest family of RapidIO building blocks to provide system architects with greater IO and processing performance for building scalable next generation programmable systems."

The RapidIO Solution
The RapidIO endpoint solution is compliant with the interconnect specification v1.1 and leverages the special features of the Virtex-II series FPGAs such as the BlockRAM, Digital Clock Managers, and the 840 Mbps LVDS I/Os to support an aggregate bandwidth of up to 8 Gbps per port. A bridge to hook up the RapidIO endpoint to the PowerPC CoreConnectTM PLB is available in the form of a reference design.

License price and availability
The RapidIO PHY and Transport/Logical Layer cores are available now as a LogiCORETM product under the terms of SignOnceTM IP license and is priced at $15,000 and $10,000 respectively.

About Xilinx
Xilinx is the worldwide leader in complete programmable logic solutions.

Previous Page | News by Category | News Search

If you found this page useful, bookmark and share it on: