9/24/2002 - Sequence Design has teamed with Silicon Metrics to produce a series of upcoming seminars to examine the challenges associated with signal integrity, and the latest tools and technologies that will be required to overcome them.
"These seminars highlight issues facing designers in sub-180nm SoC designs with a special focus on signal integrity," according to Sequence senior vice president of R&D and product marketing, Dr. Susheel Chandra. "Design closure is a big challenge as the clock frequency increases, transistor counts escalate, finer process technologies introduce their own nuances, and design cycles get compressed to satisfy time-to-market pressures."
Major Signal Integrity Issues
There are four major design-closure issues: timing, signal integrity, power, and clock. All are interdependent, necessitating a concurrent view to resolve them. Among these, however, signal integrity is the most challenging of all, manifesting itself in three ways:
Resolving these signal integrity issues calls for a blend of extraction, timing analysis, signal integrity analysis, and optimization in a single engine. Without this blend, designers might go into an iteration loop, leading to an increase in time-to-market.
Modeling will be an integral component of Sequence's signal integrity solution. "Signal integrity is a key concern for our leading-edge customers," said Dr. John Croix, chief technical officer and founder of Silicon Metrics. "Accurately producing signal integrity models adds significant complexity and substantial simulation overhead to the characterization and modeling process. Silicon Metrics solves these customer challenges with a proven and fully automated system . Silicon Metrics is currently working with customers to fully realize the productivity benefit from the new signal integrity analysis and avoidance solutions."
These seminars will cover design closure tools and methods currently available from Sequence Design and Silicon Metrics, along with an examination of new issues, such as electromigration and voltage drop, that are becoming more critical in sub-100nm designs. Specific subject areas include modeling, analysis and avoidance of coupling delay and voltage drop, hierarchical design, and concurrent design optimization.
Sequence Design, Inc., the SoC Design Closure CompanySM, enables system-on-chip designers to bring higher-performance and lower-power integrated circuits quickly to fabrication. Sequence's physical design software and solutions give its more than 100 customers the competitive advantage they need to excel in aggressive technology markets, despite demanding complexity and time-to-market issues of sub-180 nanometer designs.
Sequence has worldwide development and field service operations. The company was recently named by Reed Electronics as one of the top 50 companies to watch in the electronics industry. Sequence is privately held. Sequence is a member of Cadence Design Systems' ConnectionsTM and Mentor Graphics' Open DoorTM partnership programs.
About Silicon Metrics
Silicon Metrics' characterization, modeling, and analysis products allow customers to shorten design cycles and improve chip performance by creating best-in-class models that combine silicon predictability with designer productivity. Silicon Metrics is a privately held company with offices in Austin, Texas and San Jose, Calif. Silicon Metrics is represented by Marubeni Solutions in Japan and Tritech Systems in Korea. Company investors include Austin Ventures, Needham Capital Partners, Current Ventures, Cadence Design Systems, Inc. (NYSE: CDN), and Synopsys, Inc. (Nasdaq: SNPS).
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