Cadence Introduces Single-Architecture Encounter System for Nanometer Design

9/19/2002 - Cadence Design Systems, the world's leading supplier of electronic design products and services, introduced the Cadence® Encounter RTL-to-GDSII architecture for nanometer-scale digital design implementation. The Cadence Encounter system combines silicon virtual prototyping and detailed IC implementation into a unified architecture with a single in-memory data model and user interface. All Cadence SoC EncounterTM customers will be upgraded to version 2.2, which is based on the new architecture and leverages best-in-class nanometer technologies, including the NanoRoute graph-based routing engine and CeltICTM signal integrity analyzer.

Cadence is also introducing Nano Encounter, a new lower-cost product configuration that supports non-hierarchical designs up to 10-million-gates. SoC Encounter and Nano Encounter support a continuous convergence methodology in which design teams get full-chip detailed design implementation - including detailed routing - the first day of implementation and every day thereafter. The Encounter system is the first design architecture with the performance and capacity to deliver daily full-chip, full-wire iterations for massive nanometer designs. This wires-first approach enables design teams to always know the status of their design relative to its performance goals, to always work on the highest priority portions of the design, and to make systematic, predictable progress toward tapeout.

"The Cadence Encounter architecture is designed from the ground up to focus on the core issue in nanometer digital implementation - delivering the best wires," said Lavi Lev, executive vice president and general manager, Cadence IC solutions business. "Nanometer success will require staying as close as possible to silicon, which means moving to a wire-centric continuous convergence design methodology that is inherently efficient and predictable."

"We beta-tested SoC Encounter 2.2, and as a longtime Silicon Ensemble customer, we're pleased with Cadence's direction and progress in nanometer IC implementation," said Kazuyuki Kawauchi, general manager, Technology Development, LSI group, Fujitsu Limited. "Cadence has integrated a great deal of advanced technology into a fast, lightweight system with compelling advantages in terms of performance, capacity, and support for cutting-edge design practices. We expect to develop a lot of nanometer chips using SoC Encounter."

"After an extensive evaluation, Agilent Technologies' Networking and Computing ASIC Products Division has deployed SoC Encounter 2.2 in our nanometer design flow," said Richard Nash, High Performance VLSI Design Automation manager. "Providing full-chip timing and routing congestion feedback early in the design cycle improves schedule predictability and time to market, and also reduces overall chip design investment. The successful incorporation of SoC Encounter into our methodology is another direct benefit of our engagement with Cadence."

"S3 has successfully designed and taped-out a six-million gate multimedia chip in nanometer process geometry using the Encounter-to-NanoRoute flow," said Michael Shiuan, vice president of engineering, S3 Graphics. "The combination of the Encounter platform and the NanoRoute router provides impressive speed and capacity. We were able to route the chip flat, which not only simplified our physical analysis and design flow, but also helped us contain die size."

According to Yoshito Muraishi, deputy general manager of Kawasaki Microelectronics, Inc., Products Development and Design Department, "Kawasaki Microelectronics and Kawasaki LSI have used the Encounter-to-NanoRoute flow on multiple tape outs at 130-nanometer and other silicon geometries, including first-silicon success at 330MHz. The new Cadence SoC Encounter 2.2 provides the speed, capacity, and cross-talk optimization needed for our next-generation designs. Its hierarchical design capability is excellent. With SoC Encounter, we could dramatically reduce turn-around-time for multi-million-gate designs."

Cadence Encounter Roadmap
SoC Encounter and Nano Encounter version 2.2 are available immediately with the unified First Encounter-based user interface, CeltIC signal integrity prevention and correction, and NanoRoute nanometer routing capability. Encounter architecture integration will be complete and shipped in production by the end of 2002, including OpenAccess support, with ongoing enhancements available thereafter. Cadence is offering attractive upgrade paths, including master-key backward compatibility, for all customers with its Silicon Ensemble® family products.

Pricing and Availability
Cadence SoC Encounter hierarchical IC implementation solution, Cadence First Encounter Ultra, and Cadence Nano Encounter are available immediately for Sun Solaris and HP's HP-UX UNIX operating systems. One-year U.S. list prices start at $595,000, $350,000, and $375,000 respectively. For information about upgrade paths for customers or for international pricing, please contact a local Cadence office.

About Cadence (Cadence)
Cadence is the world's largest supplier of electronic design technologies and services. Leading computer, networking, wireless, and consumer electronics companies use the company's solutions to design electronic systems and semiconductors down to nanometer scale. IEEE, the world's largest technical professional society, honored Cadence with its 2002 Corporate Innovation Recognition award. With approximately 5,500 employees and 2001 revenues of approximately $1.4 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN.

Cadence, the Cadence logo, First Encounter, and Silicon Ensemble are registered trademarks, and CeltIC and SoC Encounter are trademarks of Cadence Design Systems, Inc.

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