Learn About Assertion-Based Verification in the Intelligent Testbench for SOC Design as Verify 2002 Gets Underway October 3

9/16/2002 - Verify 2002, a series of eight educational seminars on Assertion-Based Verification in the Intelligent Testbench for SOC Design, kicks off Wednesday, October 3, here at the Renaissance Austin Hotel.

The series continues through November 5 at select cities throughout the United States and Canada, and travels to Munich, Germany, Thursday, October 10.

Each seminar includes two featured speakers. Harry Foster, chairman of Accellera's Formal Language Committee and author of "Principles of Verifiable RTL" and the soon-to-be-released "Assertion-based Design," will present a tutorial on why, where and how to use assertions in integrated circuit (IC) designs. Anders Nordstrom, director of engineering at PacketDNA and a member of the IEEE 1364 Verilog Standards Committee and the Accellera SystemVerilog Committee, will take participants through the evolution of verification methodologies, and provide a real-world example of verification methodologies associated with advanced telecom designs.

This year's dates and locations are:

Sponsor companies and presenters include Axis Systems, CoWare, Denali Software, Forte Design Systems, Novas Software, Sun Microsystems, and Verplex Systems.

These educational seminars have been designed to help electronic engineers learn how to incorporate and use assertion-based languages and tools in their design flows and advance towards an intelligent testbench solution.

Agenda sessions include:

The Verify Seminars, which began in 1997, are free of charge to any design engineer, verification engineer or engineering manager who registers at www.verifyseminars.com

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