8/27/2002 - Mentor Graphics announced a new version of ADVance MSTM (ADMS), its single-kernel, analog/mixed-signal (AMS) simulator. ADMS includes Mach TATM for fast circuit simulation and EldoTM RF for modulated steady-state simulation. The inclusion of these technologies and other enhancements makes ADMS the industry’s most advanced, versatile, language-neutral simulator available for chip-level verification of complex AMS system-on-chip (SoC) designs.
Mentor has also been aggressively adding new functionality, enhancements and language support to ADMS to bring powerful simulation technology to the full range of next generation SoC designs—D/a, d/A and those with complex memory subsystems and RF components.
Today’s AMS SoC designs combine analog, digital and RF content more tightly than ever before. They increasingly depend on integrated analog blocks such as A/D and D/A converters, phase-locked loops, memory subsystems, RF modules and adaptive filters. Combining these diverse functions and circuit design styles puts tremendous pressure on designers. ADMS gives AMS SoC designers the ability to evaluate performance at the chip level in advance of pushing each block through its own design flow. At final chip assembly, ADMS ensures design integrity through its high performance mixed-level simulation for bottom-up functional verification at the full-chip level.
"As new functionality is added to consumer electronics, the amount of analog content on mixed-signal SoCs increases exponentially. The ability to do top-down design and bottom-up verification gives companies a tremendous advantage in the marketplace," said Jue-Hsien Chern, vice president and general manager, deep sub-micron division, Mentor Graphics. "With Mentor’s extension of ADMS to include Mach TA and Eldo RF, we give designers a technically advanced simulation tool that is unmatched by anyone in the industry."
Mach TA—Fast, Transistor-level Simulation
Mach TA is an accelerated simulation engine that accurately verifies transistor-level timing for large digital blocks/components up to 1,000 times faster than SPICE-based circuit simulators. Using innovative algorithms, Mach TA delivers the superior speed, accuracy and capacity needed to help designers determine if SoCs they are designing meet detailed timing specifications. Input for Mach TA is a standard SPICETM netlist.
ADMS with the Mach TA engine has proven in benchmarks on a wireless modem design to be as much as nine times faster than a standard co-simulation solution. It was also able to complete simulation of a complex clock circuit in one hour, as compared to one month with traditional co-simulation.
Eldo RF—High-speed RF Simulation
Eldo RF is a high-speed, high-performance simulation engine built upon the Eldo analog simulator, featuring algorithms that can complete full-chip RF IC verification for wireless applications.
Eldo RF provides the necessary algorithms to efficiently handle the RF blocks in typical transceivers, such as low noise amplifiers, mixers or voltage-controlled oscillators. Its frequency or time/frequency-based algorithms, such as the steady-state analysis and modulated steady-state analysis, provide accelerated simulation for these critical blocks operating at the highest frequencies, typically several GHz. With Eldo RF integrated into the ADMS simulation environment, ADMS can now run in a mode where the modulated steady-state analysis algorithm is used to efficiently handle high-speed digitally modulated signals.
This integrated solution allows efficient simulation of communications systems that contain tight feedback loops between an RF front end and baseband systems featuring complex digital signal processing (DSP) functions.
ADVance MS—Language Neutrality Speeds SoC Simulation
ADMS is the only true single-kernel, language-neutral simulator available today and combines four high-performance simulation engines in one efficient tool: Eldo for general purpose, large signal model simulations; ModelSim® for digital simulations; Mach TA for fast transistor-level simulations; and Eldo RF for modulated steady-state simulation. ADMS uses a single netlist hierarchy and allows designers to freely combine VHDL, Verilog, VHDL-AMS, Verilog-AMS, SPICE and C anywhere in the design. This enables both top-down design and mixed-level simulation for bottom-up verification.
Mentor Graphics Integrated AMS SoC Design Tools
Mentor Graphics delivers superior technology for AMS SoC design, from capture and simulation through physical implementation, verification and analysis. The tool set includes the Design Architect®-IC tool, with a powerful AMS SoC design cockpit, and the IC Station® chip assembly solution, for physical layout, top-level floor planning and routing. ADVance MSTM is a single-kernel, language-independent simulation environment for digital, analog, mixed-signal and RF circuits. Finally, the Calibre® and Calibre xRCTM tools deliver the industry’s highest capacity, performance and accuracy for physical verification and parasitic extraction. This fully integrated set of tools is available immediately for Linux, HP and Sun platforms.
About Mentor Graphics (www.mentor.com)
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $600 million and employs approximately 3,700 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314.
Mentor Graphics, Design Architect, IC Station, Calibre, ModelSim and xCalibre are registered trademarks and ADVance MS, Mach TA, Calibre xRC and Eldo are trademarks of Mentor Graphics Corporation.
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