8/27/2002 - Mentor Graphics introduced a major new release of its front-to-back IC design tools for analog/mixed-signal (AMS) system-on-chip (SoC) designs. The increasing demand for more complex features in consumer electronics has fostered exponential growth in the amount of analog content on mixed-signal SoCs. In order to address the challenges of these chips, Mentor Graphics has made AMS SoC design tools a core focus, and has added functionality to existing tools while developing cutting-edge new tools. With its industry-leading solutions, Mentor Graphics now offers the most complete IC design flow to ensure success for designers creating complex AMS SoC designs.
"To stay ahead of the growing complexity we’re seeing in today’s SoC designs, we selected Mentor’s design methodology because we were able to create a single netlist containing data from multiple sources, then simulate at different levels of abstraction," said Rami Ahola, senior RF design engineer at Spirea AB. "The Mentor tools have also allowed us to apply the unique techniques we’ve developed to maximize CMOS processing capabilities for RF circuits."
"This is a significant release for Mentor Graphics and our customers," said Jue-Hsien Chern, vice president and general manager, deep sub-micron division, Mentor Graphics. "We’ve made dramatic engineering advances in our products, which ensure our customers will continue to meet the increasingly complex challenges of the AMS SoC design space. Our strategy has been to develop technologically superior tools for all phases of the design flow, and this is very apparent in this release."
The Mentor Graphics® AMS SoC flow includes Design Architect®-IC (including a new AMS SoC design cockpit), ADVance MSTM (single-kernel simulator for analog, digital, transistor-level and RF simulation), IC Station® (physical layout and implementation), Calibre® (the industry standard for physical verification) and Calibre xRCTM (a new full-chip, transistor-level parasitic extraction tool). All tools are available immediately.
Mixed-Language, SoC Design Cockpit
One of the major challenges in traditional design flows has been the separate, isolated development of analog and digital subsystems, wherein the integration of these components does not take place until layout, and testing occurs after fabrication. Because of this, AMS SoC design, verification and simulation have become slow, expensive and error-prone.
Design Architect-IC now offers a new, multi-level, multi-language IP management environment for the setup of complex simulations, in addition to schematic-driven layout and cross-probing. This SoC design cockpit brings together design components created with analog, digital and mixed-signal hardware description languages (HDLs), including VHDL, Verilog, VHDL-AMS and Verilog-AMS, as well as transistor-level schematics. Design Architect-IC assembles the multi-format design data, then enables the creation of a single netlist for verification of all components.
High-Performance, Single-Kernel Simulation Technology
As analog and RF content continues to increase in today’s SoC designs, simulation has become a bottleneck in the design process. To solve this problem, the new version of ADVance MS combines four powerful simulation technologies, which gives designers the ability to choose the appropriate simulation engine for the various design components. ADVance MS consists of the ModelSim® tool for digital simulation, the EldoTM tool for large signal model simulation, the Mach TATM tool for fast circuit simulation and Eldo RF for modulated steady-state simulation.
Physical Verification—The Industry Standard
Calibre’s physical verification tool suite, Calibre DRCTM and Calibre LVSTM, ensures that integrated circuit (IC) physical designs conform to foundry manufacturing rules and match the intended functionality of the chip. Calibre features design style-independent execution to provide optimal performance on designs ranging from random access memories to SoCs using a single, qualified rule file. Calibre also provides advanced debugging capabilities, including intuitive error reporting, a graphical results viewing environment and hierarchical error isolation. The combined force of design style independence and advanced debugging extend Calibre’s world-class run time performance to further reduce verification time by simplifying tool set-up and error correction.
Full-Chip Parasitic Extraction
Because process geometries keep shrinking, accurate parasitic data for the entire design is absolutely crucial in order to achieve accurate post-layout simulation. Newly introduced today, Mentor Graphics Calibre xRC is the only extraction solution available that enables transistor-level extraction for all circuit types. Historically, designers have been forced to use different extraction tools for different types of circuits. Calibre xRC combines the proven performance and capacity of the Calibre hierarchical engine with the accuracy and layout vs. schematic (LVS) integration of xCalibre® to handle the full range of circuit types found in AMS SoC designs (analog, memory, custom, etc).
The Mentor Graphics AMS SoC tools are designed to work best when used together, but Mentor also believes in interoperability and industry standards versus proprietary databases and data formats. Thus, the tools can also be individually inserted into any design flow with minimal disruption to the company’s existing methodologies.
All of the Mentor Graphics AMS SoC design tools are Linux compatible, which offers users dramatic savings in infrastructure costs, along with increased performance. The tools also operate on Sun and HP platforms.
About Mentor Graphics (www.mentor.com)
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $600 million and employs approximately 3,700 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314.
Mentor Graphics, Calibre, xCalibre, Design Architect, IC Station, and ModelSim are registered trademarks and ADVance MS, Calibre xRC, Eldo, Calibre DRC, Calibre LVS and Mach TA are trademarks of Mentor Graphics Corporation.
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