8/16/2002 - Sequence Design received a patent for on-chip interconnect inductance modeling, an essential technology to insure SoC signal integrity. The newly patented technology has already shipped to customers as an additional capability within Columbus-RF, Sequence's award-winning interconnect extraction tool.
Tuned specifically for high-frequency designers, Columbus-RF features industry-leading modeling capabilities for RC and inductance in RF circuits. The tool's tight integration with the industry-standard Cadence Analog Design Environment and physical verification tools ensures ease of use and ease of adoption.
U.S. Patent No. 6,381,730, "Method and System for Extraction of Parasitic Interconnect Impedance Including Inductance," describes a comprehensive system for generating accurate RLC models for interconnect lines. By using these models, SoC designers can accurately calculate line signal delays without using complex 3-D field solvers. The new methodologies in the patent are based on the work of co-authors, Dr. Keh-Jeng (K.J.) Chang, Dr. Li-Fu Chang, Dr. Robert Mathews, and Dr. Martin Walker, all of Sequence Design.
According to Dr. K.J. Chang, Sequence vice president of research, this marks the first time these techniques have been patented. "It is a real breakthrough to provide this type of inductance modeling," he said. "Automated 3-D inductance extraction is essential for SoC design teams to deal with SI and power-distribution issues."
In addition to covering inductance modeling, the patent also provides techniques for the synthesis of RLC netlists for circuit-level simulation and back-annotation, allowing designers to view all parasitic effects on the circuit simultaneously.
"Inductance is becoming even more critical at 130 nanometers while we continue to expand our patent portfolio in this area. The production-proven Columbus-RF already employs this patented technology for modeling line and mutual inductances required for time-domain simulations in RF and high-speed digital ICs," said Vic Kulkarni, Sequence president and CEO. "We look forward to continuing to offer this essential technology to the designers of communications ICs."
Columbus-RF is part of Sequence's ExtractionStage, a suite of high-performance EDA tools tuned for complex multi-million-gate SoCs (systems-on-a-chip) and analog/mixed-signal design. ExtractionStage is the only suite of interconnect parasitic tools extracting high-accuracy resistance (R), coupled-capacitance (C), and inductance (L) values across a wide range of design styles. The product has experienced significant sales growth in the past two years, gaining more than 20 customers since its release. IBM includes Columbus-RF in its SiGe design kits, and Qualcomm, Valence, and LeCroy are among a growing list of customers using the product for wireless design. Columbus-RF was recently chosen by the readers of Wireless Systems Design as the best wireless design tool for 2002.
About Sequence (www.sequencedesign.com)
Sequence Design, Inc., the SoC Design Closure CompanySM, enables system-on-chip designers to efficiently bring higher-performance and lower-power integrated circuit designs quickly to fabrication. Sequence's design software and solutions give its more than 100 customers the competitive advantage they need to excel in aggressive technology markets, despite demanding complexity and time-to-market issues of sub-180 nanometer designs.
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