8/13/2002 - Mentor Graphics introduced the SpeedGate DSVTM (Direct System VerificationTM) 2.0 tool, the latest version of its in-circuit application-specific integrated circuit (ASIC) verification environment. The SpeedGate DSV tool uses off-the-shelf field-programmable gate arrays (FPGAs) to create ASIC prototypes that can be tested at speeds comparable to a real-time operating environment. Version 2.0 adds distributed processing interfaces to accelerate compute-intensive operations, such as synthesis and place and route, driving down costs by reducing the time for those steps in direct relation to the amount of compute farm resources utilized. The new version also expands language support to include Verilog, VHDL and mixed-HDL.
"The SpeedGate DSV tool is extremely popular with our customers because it offers advanced ASIC verification features, from design to prototype," said Harish Balan, product marketing manager, SpeedGate DSV, Mentor Graphics. "With version 2.0 Mentor Graphics has accelerated the verification cycle further by adding load-sharing capabilities that allow designers to concurrently perform compute-intensive tasks that until now have consumed much of the total verification time."
Multiple Distributed Processing of Compute-Intensive Operations
The SpeedGate DSV 2.0 product includes integrated support for Platform Computing's LSF (Load Sharing Facility) and Sun Microsystems Grid Engine, allowing designers to distribute compute-intensive operations, such as synthesis, across clusters of workstations. Direct interfaces to load-sharing tools allow parallel submission of synthesis jobs for faster, complete module synthesis. The technology can also extend to speed up place and route processing. Faster synthesis and place and route operations lead to faster prototype development and a significant reduction in total verification time.
"Platform Computing works closely with Mentor Graphics to provide integrated solutions that maximize productivity and accelerate time-to-market for designers," said Paul Hill, vice president, marketing and business development, Platform Computing. "With our distributed software solutions, complex tasks can be shared across multiple workstations, shrinking verification times significantly and ensuring productivity in a complex and competitive industry."
Expanded Language Support
The SpeedGate DSV 2.0 product now supports Verilog, VHDL and mixed-HDL designs, enabling design teams to prototype all types of designs. The input HDL is read into the SpeedGate DSV 2.0 partitioning technology that works on a unified database. The design is then decomposed into its individual logic blocks and can then be effectively partitioned across multiple FPGA devices through unconstrained manipulation of the design hierarchy.
About SpeedGate DSV
The SpeedGate DSV tool is the most comprehensive and extensible solution for all aspects for the prototype design flow - partitioning, debug and interconnect, also linking to board creation and analysis tools. An interactive design cockpit launches partitioning and synthesis tools, and the completely scriptable interface plugs into any ASIC design environment - working hand-in-hand with emulation and gate-level simulation.
The SpeedGate DSV tool includes patent pending advanced partitioning technology that enables designers to minimize the number of FPGAs used to prototype a design. The SpeedGate DSV tool fully supports the prototyping process with a team design environment, including sophisticated check-in/check-out features that track source code changes and manage version control.
Pricing and Availability
The SpeedGate DSV 2.0 tool is available now at a price of $98,500 for a floating license; the upgrade from the SpeedGate DSV 1.0 tool is free to existing customers. The SpeedGate DSV tool supports Sun Solaris 2.7 and 2.8 and supports ASIC partitioning to Xilinx FPGAs. More information can be found at www.mentor.com/speedgatedsv. LSF from Platform Computing and Sun Microsystems Grid Engine are sold separately.
About Mentor Graphics (www.mentor.com)
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $600 million and employs approximately 3,700 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314.
Mentor Graphics is a registered trademark and SpeedGate DSV and Direct System Verification are trademarks of Mentor Graphics Corporation.
Previous Page | News by Category | News Search
If you found this page useful, bookmark and share it on: