8/12/2002 - M-TEC WIRELESS used Celoxica's DK1 design suite in the development of a custom processor for its widebeamTM modules. With DK1, M-TEC was able to re-implement a processor design in an FPGA using Celoxica's Handel-C hardware programming language that was 50 per cent faster overall and 30 per cent faster than in VHDL.
Wind River Systems, Celoxica's global distribution partner, introduced M-TEC to the idea of implementing low-level algorithms such as MAC processing in FPGAs using DK1. "At our first meeting with Celoxica the company demonstrated a Spartan II based design in which a complex 3D graphics model was being rotated while live video input was being texture-mapped to its surface. You could not have designed such functionality into a 200,000 gate FPGA using VHDL. I don't believe that C is a good language for hardware design because it lacks parallel expression. But I could see that the parallel and timing extensions from Occam that Celoxica had applied to ANSI-C in developing the Handel-C hardware programming language were going to be especially valuable. I visited Celoxica's headquarters. While there, I re-implemented our existing VHDL solution using the DK1 suite in just one day. I was hooked," said Jan Mennekens, chief technical officer at M-TEC WIRELESS.
The design challenge
M-TEC's widebeamTM broadband wireless LAN modules are configurable for HiperLAN/2, IEEE 802.11a++, wireless Ethernet and HiSWANa standards, achieving speeds of up to 54 Mbps and higher. The modules integrate transmitters and receivers together with protocol interfaces and a processing section that provides extra calculations such as error detection & correction, encryption/decryption and insertion of extra payload information.
Most of these operations are manageable by software on general processors, but market demand for higher performance and flexibility, smaller size, lower cost and power consumption led the company to look at integrating the key bottleneck functions directly in hardware.
"We wanted a new design in which high-level software sat above lower-level digital functions, and the OFDM modem layer at the base of the stack. This led us quite naturally to a basic partitioning of the design. Timing requirements are measured in milliseconds for the high-level functions, but we need to get into the 100ns region for lower level algorithms. That led us straightaway to decide on dedicated hardware for the fastest functionality, and software running on a standard CPU for higher levels," said Mennekens.
The design solution
M-TEC chose FPGAs as the hardware platform because production volumes could not justify the NREs associated with going to an ASIC. FPGAs also provided additional benefits such as faster time to hardware implementation with the flexibility of not being forced down the route of one specific protocol.
"Before meeting Celoxica, we were using familiar VHDL tools to design a core for data movement. An advantage of giving the FPGA a processor-like core is that top-level CPU software and MAC processing hardware can communicate readily via shared memory and a simple interrupt line. There is no need for complex interfacing," explained Mennekens.
Mennekens continued: "Designing a new core was a difficult route to follow but we could not find a suitable DMA engine that could move data at rates in excess of 50Mbps with the intelligence of a processor, and processors within our target price range did not move data fast enough. So we decided to design our own hybrid core with DMA performance and processor intelligence. With several iterations and simulations this took us around six months to perfect in VHDL."
M-TEC WIRELESS bought a Celoxica-supported DK1 design suite license. The resulting design was both smaller and faster than the original VHDL. With around 400 lines the Handel-C code is 50 per cent smaller than the VHDL code, even including the extensive commenting and documentation. The Handel-C design also runs significantly faster, requiring around four clock cycles per instruction compared with VHDL's eight - and can be clocked at around 120MHz compared with 80MHz of the VHDL implementation.
"For the core, we couldn't have done better than Handel-C," concluded Mennekens. "On the other hand, we felt that for interfacing to external hardware it would be better to use VHDL to design the actual interfaces and then Handel-C to hook them up."
The DK1 design suite targets the design, validation, iterative refinement and implementation of complex algorithms in hardware. It includes built-in design entry, simulation, and synthesis - all driven by Handel-C, a design-entry language based on ANSI-C that combines parallelism with a central timing model. Developers with knowledge of the C programming language find DK1's Handel-C language simple to use. With its intuitive hardware-specific constructs, Handel-C lets software developers quickly code hardware designs.
DK1's integrated Handel-C-to-gate-level synthesis and optimisation eliminates the need for any interim HDL stage or the need to maintain any additional code stream. The integrated Handel-C compiler lets developers generate optimised EDIF netlists appropriate for targeting FPGAs using FPGA manufacturers' tools.
About M-TEC WIRELESS (www.mtecwireless.com)
M-TEC WIRELESS designs and markets widebeamTM modules, using 5 GHz and OFDM technology, to build next-generation broadband wireless LANs. The widebeamTM modules are geared towards OEM manufacturers of residential gateways, WLAN access points, Network Interface Cards, CATV access points, set-top boxes etc. The modules are software configurable to support both HiperLAN/2 and IEEE 802.11a. M-TEC WIRELESS is a spin-off of the M-TEC GROUP. The group designs and delivers network solutions for broadband telecom networks and industrial power infrastructures and has more than 50 years experience in developing new technology and successfully turning it into commercial products. The group evolved originally from designing industrial power networks to state-of-the-art broadband telecom networks. Building wireless abilities followed naturally.
About Celoxica (www.celoxica.com)
Celoxica brings software methodologies to hardware design with tools that converge electronics design automation (EDA) and embedded software development (ESD) to improve designer productivity, address design skills shortages, and overcome system performance bottlenecks.
The company's design tools, and their supporting products and services, introduce three aspects of software development to the hardware design process: a C-based language for rapidly describing the functionality rather than the underlying structural detail of the hardware; an integrated development environment (IDE) for hardware design with features such as symbolic debugging as well as synthesis that correlates to software compilation in that it is very fast; and libraries of predefined functions including access to peripherals and processors in hardware via common APIs.
Celoxica has alliances and partnerships with Altera Corporation, Avnet Design Services, Wind River Systems Inc. and Xilinx, Inc. The company is headquartered in Abingdon, UK, with additional offices in Campbell, California, USA; Yokohama, Japan; and Singapore.
Celoxica and the Celoxica logo are the trademarks of Celoxica Limited.
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