7/30/2002 - For IC designers who require not only area-efficient, but highly integrated and power-efficient system-on-chips (SoCs), Virage Logic, Corp. (Nasdaq: VIRL), a global leader in embedded memory, today announced its Ultra Low Power (ULP) embedded memory platform. In this initial release, there are two new SRAMs and a ROM. The Area, Speed and Power (ASAPô) ULP Single-Port SRAM and the Self-Test and Repair (STARô) ULP Single-Port SRAM and STAR ULP ROM utilize an architecture that consumes four to 26 times less active power than competing products.
With the explosion of wireless and portable electronic devices, designers want to dramatically reduce the active and standby power consumption to extend battery life, which is a key driving force behind many Bluetooth and 802.11b devices, as well as mobile devices such as cell phones, PDAs or laptops. As the first IP company to cost-effectively deliver a ULP embedded memory platform on Taiwan Semiconductor Manufacturing Company's (TSMC) 0.18- and 0.13-micron logic processes, Virage Logic combines low power and high performance into a single-chip solution. Through built-in features that allow power management and power minimization, the ULP SRAMs and ROM embedded memories are targeted for sub-megabit (Mb) to multi-megabit designs.
"The Virage Logic ULP memories are ideal for our ultra-miniature, ultra-low power, software-programmable, digital signal processing (DSP) technology," said Todd Schneider, vice president of technology, Dspfactory. "Our target markets of cellular phones, PDAs, hearing aids, headsets, and other portable, battery-powered DSP-based products demand high performance along with very low power consumption and the ULP memories from Virage Logic are a perfect fit."
With an efficient power management implementation, the memories are divided into sub-sections called banks. When the memory is in use, one or more banks become active, while the inactive banks are turned off, thus reducing active power consumption. In addition, within the inactive banks, the clock signal is turned off, further reducing power consumption. Because the memories include separate schemes for controlling read and/or write operations, the power can be shut off as soon as the read or write operation is completed.
Through power minimization techniques such as banking, latched sense amplifiers and divided wordlines, the ULP platform delivers a way to decrease size, and increase application speeds, while consuming less power. Banking accounts for lower capacitance because of the shorter bitlines in each bank. This results in not only a decrease in active power consumption, but a speed increase. In addition, the sense amplifiers are used to detect and amplify changes in the voltages of signals within the memory. Because Virage Logic's implementation allows the detection and amplification of a transition with minimal change in voltage, it is faster and consumes less power. To further reduce power, Virage Logic employs a divided wordline scheme -- at a particular time only half of the bitlines of a specific wordline are active, thus reducing the bitline power in half.
"Because of our architectural innovation around power management and power minimization, the ULP embedded memories allow users, for the first time to eliminate the need for expensive packaging and additional thermal management," said Shakeel Jeeawoody, product marketing manager, Virage Logic. "With our silicon-proven differentiated memory architecture, now our customers can easily include embedded memories in their designs while meeting required power budgets."
For the ASAP and STAR ULP SRAMs, the combination of banking, plus divided wordlines enable the memories to operate at 0.046mW/MHz worst case for a 256 kilobit (Kb) memory. In addition, the generated ULP SRAMs range from 128Kb to 512Kb. For the STAR ULP ROM, it is the reduction in standby leakage in the memory that delivers the biggest breakthrough in terms of saved power consumption which is by 1,706 percent (0.031mW/MHz worse case for a 1Mb memory). Geared towards applications that require megabits of memory, STAR ULP ROMs can be generated ranging from 64Kb to 16Mb.
"TSMC's collaboration with Virage Logic gives our mutual customers access to compilers optimized for portable applications," said Kurt Wolf, director of IP and library marketing at TSMC. "Cost-effective, next generation SoC designs for wireless and consumer products will require integration of large amounts of repairable memory in a power-efficient environment. Virage Logic's new ULP platform makes both possible."
The STAR SRAM and ROM will also be available as part of Virage Logic's newly announced Re-configurable STAR Memory System, providing a comprehensive test and repair solution for these memories when embedded in multi-megabit quantities. The company now extends its technology for increasing yield and lowering total manufacturing costs to the ROM products as well.
Availability and Pricing
The SRAM embedded memories will be available first on TSMC's 0.18- and 0.13-micron logic processes, while the ROM will be available first on TSMC's 0.13-micron process with front-ends available today and ready-to-manufacture silicon between now and the end of the fourth quarter of 2002. Pricing for the ASAP ULP SRAM starts at $57,000 (U.S. list price); STAR ULP SRAM pricing starts at $130,000 (U.S. list price); the STAR ULP ROM starts at $200,000 (U.S. list price).
About Virage Logic
Virage Logic (Nasdaq: VIRL) is a global leader in embedded memory. To meet customer design goals with the highest level of quality, Virage Logic products are silicon proven and production ready, and optimized for area, power and speed. These products include embedded memory cores, as well as software tools and custom memory design services. The company's customers include fabless semiconductor companies who use pure-play foundries and other semiconductor companies. The company has over 200 employees and is located at 46501 Landing Pkwy., Fremont, Calif., 94538. Telephone: (877) 360-6690 (toll free) or (510) 360-8000. Fax: (510) 360-8099.
SAFE HARBOR STATEMENT FOR VIRAGE LOGIC UNDER THE PRIVATE SECURITIES LITIGATION REFORM ACTOF 1995:
Statements made in this news release other than statements of historical fact are forward-looking statements, including, for example, statements relating to Virage Logic's business outlook, new products and new relationships. Forward-looking statements are subject to a number of known and unknown risks and uncertainties, which might cause actual results to differ materially from those expressed or implied by such statements. These risks and uncertainties include Virage Logic's ability to maintain and develop new relationships with third-party foundries, adoption of technologies by semiconductor companies and increases in the demand for their products, the company's ability to overcome the challenges associated with establishing licensing relationships with semiconductor companies, the company's ability to obtain royalty revenues from customers in addition to license fees, business and economic conditions generally and in the semiconductor industry in particular, competition in the market for embedded memories and other risks including those described in the Company's Annual Report on Form 10-K for the period ended September 30, 2001, filed with the Securities and Exchange Commission (SEC) on December 19, 2001, and in Virage Logic's other periodic reports filed with the SEC, all of which are available from Virage Logic or from the SEC's website (www.sec.gov), and in press releases and other communications. Virage Logic disclaims any intention or duty to update any forward-looking statements made in this news release.
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