Synopsys Announces DesignWare Memory IP Subsystem Solutions

7/10/2002 - Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex integrated circuit (IC) design, today announced the immediate availability of a full line of memory intellectual property (IP), which includes memory models, memory controllers, and memory BIST. The memory solution, as part of the DesignWare® IP Library is available to designers through a single license and price, with no per-use fees or royalty payments.

The DesignWare IP Library provides a suite of memory IP designed to work together seamlessly in any design. The ability to use pre-designed, pre-verified IP blocks is key in enabling designers to dramatically reduce the time spent creating and verifying memory subsystems. The silicon-proven DesignWare memory solution ensures designers have access to the highest performance, easiest-to-integrate IP available.

"We successfully met our 150 MHz system operating frequency with the DesignWare Memory Controller, which integrated smoothly into our design environment," said Subbu Muddappa, staff design engineer, Woodside Networks. "The complete verification solution, including Synopsys DesignWare with simulation memory models for SDRAM and Flash, enabled us to verify our entire wireless LAN solution quickly and efficiently."

DesignWare Memory IP Solution
The DesignWare Memory Controller is a fully configurable, synthesizable memory controller for dynamic and static memories. A single memory controller can support multiple memory types such as DDR-SDRAM, SDR-SDRAM, Mobile-SDRAM, Micron SyncFlash, SSRAM, SRAM, Flash and ROM devices. The memory controller interfaces to the system via an AMBA® AHB 2.0-compatible interface and may also interface with other buses through a simple gasket.

The number of pre-verified memory simulation models in the DesignWare IP Library is constantly growing, with more than 10,000 models covering more than 25 memory vendors' devices available today. The models integrate with simulators through the industry de facto standard SWIFT interface, which is supported by all Synopsys simulators and by all other major simulator vendors.

DesignWare Memory BIST is a fully configurable, synthesizable solution for built-in self-test of embedded SRAM and ROM memory structures. The DesignWare Memory BIST solutions increase overall product quality by ensuring fault coverage of embedded memory defects through built-in algorithmic testing. In order to reduce test time and maximize utilization of embedded test resources, tests are executed in parallel with a shared BIST controller. Four industry-standard SRAM BIST algorithms are available and can be selected at runtime: March LR, March C-, MATS++, and a retention test using a pause-polling mechanism.

"We have consistently heard from our customers that acquiring individual pieces of memory IP is becoming cost prohibitive," said Ed Bard, director of DesignWare marketing at Synopsys. "The Synopsys DesignWare IP Library gives designers immediate access to an entire memory portfolio for a single price. The thousands of designers who already have access to the DesignWare IP Library can get the newly available memory IP by simply downloading it from the DesignWare Memory Central Web site."

Access to the full suite of memory IP is made available through DesignWare Memory Central; a new memory-focused Web site that lets designers download DesignWare Memory IP and documentation. A current DesignWare license is required in order to download. Visit Memory Central at:

About Synopsys
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at

Synopsys and DesignWare are registered trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

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