7/3/2002 - Xilinx, Inc. (NASDAQ:XLNX) today announced the availability of the 644MHz Single Data Rate (SDR) Low Voltage Differential Signaling (LVDS) solution for SerDes Framer Interface (SFI)-4 and 10 Gigabit Sixteen Bit Interface (XSBI) applications based on Xilinx® Virtex®-II and Virtex-II Pro Platform FPGAs. Designers of 10 Gigabit Ethernet and OC-192 SONET/SDH systems now have access to an off-the-shelf, flexible solution for addressing XSBI and SFI-4 interfacing requirements. Leveraging the powerful features of the Virtex-II FPGA series, such as digital clock managers (DCM), abundant Block RAM, and flexible and scalable LVDS I/Os, designers can now achieve the maximum performance required for SFI-4 and XSBI applications. For more information about this design or other Xilinx SystemIO solutions, visit www.xilinx.com/connectivity.
"With the high-performance LVDS I/Os in the Virtex-II and Virtex-II Pro FPGA, we continue to provide ready-to-use, leading-edge interface solutions to our customers implementing SFI-4 and XSBI interface requirements," said Andy Debaets, senior director of Systems and Application Engineering at Xilinx. "The highly flexible and scalable SelectLVDS™ reference design provides a seamless interface to the third party framer and enables our customers to achieve maximum performance for their OC-192 SONET/SDH and 10 Gigabit Ethernet system designs."
Xilinx SelectLVDS Reference Designs
The 644 MHz SDR SelectLVDS reference design (http://www.xilinx.com/xapp/xapp622.pdf) provides system designers with a ready-to-use solution for the SFI-4 interface to seamlessly interface to the external OC-192 SONET framer and optic modules at 622 Megabit Per Second (Mbps). Additionally, the reference design supports both 622Mbps and 644 Mbps data rates for direct SFI-4 and XSBI interfacing to the respective external 10Gbps SONET and Ethernet devices. Xilinx is the first company to provide a complete checklist to ensure the reference design is compatible with the OIF SFI4-0.10 specification and the IEEE P802.3ae Draft 4.1 specification as part of the detailed application note.
Xilinx also offers a fully scalable and flexible 840Mbps Double Data Rate (DDR) SelectLVDS reference design (http://www.xilinx.com/xapp/xapp265.pdf), allowing designers to implement the 16-bit LVDS channel in any location. The reference design is ideally suited for data traffic aggregation applications. To help designers implement applications such as high speed interfacing between a network processor unit (NPU) and a traffic manager, up to 7 groups of 16-bit transmitter/receiver blocks can be instantiated into a single Virtex-II Platform FPGA. The 840 Mbps reference design also provides multiple-channel options (4b, 16b or 20b) and is optimized for the Virtex-II Platform FPGA.
License Price and Availability
Both reference designs are available now and are downloadable free of charge from Xilinx.com as part of the complete Xilinx Platform FPGA SystemIO solutions. Xilinx Platform FPGA SystemIO solutions address a wide variety of system interconnectivity standards including related IP cores, design services and reference designs from both Xilinx and third-party providers.
About the Xilinx Metro-Optical Networking Forum
Sponsored by Xilinx, Avnet Design Services and Silicon, an Avnet Company, the Metro-Optical Networking Forum is a free, one-day event that will address the challenges of designing and developing products for metro area and edge access networks. On July 25, 2002, attendees will hear from industry experts on where this dynamic market is headed, technologies driving success in the MAN space, and see forward thinking solutions developed by cutting-edge companies. Locations and agenda information can be found at www.xilinx.com/metro
Xilinx, Inc. (NASDAQ: XLNX) is the worldwide leader of programmable logic solutions. Additional information about Xilinx is available at www.xilinx.com
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