6/25/2002 - Actel Corporation (Nasdaq: ACTL), a supplier of innovative programmable logic solutions, announced the availability of version 2.2 of its Actel LiberoTM integrated design environment for field-programmable gate array (FPGA) development and design. Designers using the Libero 2.2 design environment will leverage enhanced tools for synthesis and test bench generation from Synplicity and SynaptiCAD, respectively. Actel's own place-and-route and verification tools have also been updated. These enhancements offer designers greater ease of use, streamlined product design cycles and decreased time-to-market when designing next-generation FPGA solutions.
"With new versions of industry-leading tools from Actel, SynaptiCAD and Synplicity, Libero tool suite makes it easier for designers to quickly reach their aggressive performance and logic utilization goals," said Saloni Howard-Sarin, tools marketing director at Actel. "With this announcement, Actel continues its commitment to provide quality support for Actel's FPGA families and to deliver a complete design environment that yields substantial time-to-market advantages for our customers."
Enhancements to Actel Libero Design Environment
Libero 2.2 tool suite leverages the fast, incremental timing analysis engine and automated register re-timing feature in the Synplicity Synplify software, making timing estimations even more accurate and producing highly optimized circuits with fewer design iterations. With automatic re-timing, the Synplify software eliminates the labor- intensive process of analyzing critical paths and changing HDL code to balance delay and can automatically reposition registers within combinatorial logic to balance routing and ultimately improve circuit performance.
"We are pleased Actel chose to include the Synplify synthesis product in its comprehensive Libero design environment," said Jeff Garrison, director of marketing for FPGA products at Synplicity. "With the Synplify software's high-performance timing engine and device-specific mapping technology, we believe we are able to provide synthesis technology with extremely fast runtimes and the ability to synthesize high capacity designs, allowing designers to bring their complex FPGA products to market quickly."
For test bench generation and management, Libero 2.2 design environment integrates SynaptiCAD's WaveFormer Lite version 8.3, a graphical entry tool that allows the user to describe the stimulus for the simulation graphically and then, convert the graphical information into a VHDL or Verilog test bench. WaveFormer Lite includes support for VHDL generic statements as well as VHDL attributes for specifying port size. In Verilog, clocks are defined in separate modules, reducing the size of the generated code and improving readability. The tool also handles much larger files via SynaptiCAD's new btim binary waveform file format.
"Working closely with Actel, WaveFormer Lite was designed to both strengthen and fit seamlessly into Actel's Libero integrated design environment," said Dan Notestein, president of SynaptiCAD. "A flexible and easy-to-use test bench generation system, WaveFormer Lite enables designers to bring products to market faster with dramatically improved quality of results."
Also included in Libero 2.2 design environment, Actel's enhanced Actel Designer R1-2002 software solution contains new user-friendly productivity tools to accelerate and automate the system design process without forcing the designer to relinquish control. Designer software now delivers robust power analysis, allows hierarchical netlist viewing and provides support for fixed pins. Further, designers of Actel devices using Libero 2.2 tools are now able to directly import a structural design into the design environment. Libero tool suite also converts the schematic blocks into HDL and imports all the files needed into Actel Designer software. This feature eliminates the need for the customer to manage its own data files and track which files must be passed from one tool to the next.
Additionally, Actel's Silicon Explorer II software, a verification and logic analysis tool for real-time, in-system internal device probing, has been upgraded to deliver test and debug support for additional Actel FPGA devices.
In addition, other new features have been added to Actel Libero 2.2 integrated design environment to assist designers. Libero tool suite allows users to assign and reassign different stimulus files to a given block, thereby enabling the designer to run different stimulus on the same design block. Libero design environment also supports HTML Help on Windows-based platforms, providing users with access to enhanced online help.
About Actel Libero Design Environment
Actel Libero comprehensive design environment integrates industry- leading design tools and streamlines the design flow; manages all design and report files; and passes necessary design data between tools. Libero tool suite supports mixed-mode design entry input, giving designers the choice of mixing either high-level VHDL or Verilog HDL language blocks with schematic modules within a design. This capability is especially valuable for designers integrating intellectual property (IP) into complex FPGAs where time-to-market and productivity requirements are stringent.
Actel Libero design environment includes best-in-class tools such as Innoveda's ViewDrawTM schematic capture tool; SynaptiCAD's WaveFormer Lite 8.3 test bench generation system; Mentor Graphics' ModelSim® simulation and design verification software; Synplicity's Synplify 7.1 synthesis software; and Actel's Silicon Explorer verification and logic analyzer tool and Actel Designer place-and-route software.
Pricing and Availability
Libero 2.2 integrated design environment is available in three versions: Platinum, Gold and Silver. Libero Platinum tool suite is a complete solution with unlimited design capacity and customer support and is priced at $2,495. For users designing system-level devices of 50,000 gates or less, Actel offers its Libero Gold version, which is priced at $995. The Libero Silver and Evaluation versions may be used by qualified designers for one year and 45 days, respectively, free of charge via the Actel Web site. For more information, please contact Actel.
Actel Corporation is a supplier of innovative programmable logic solutions, including field-programmable gate arrays (FPGAs) based on antifuse and flash technologies, high-performance intellectual property (IP) cores, software development tools and design services targeted for the high-speed communications, application-specific integrated circuit (ASIC) replacement and radiation-tolerant markets. Founded in 1985, Actel employs approximately 500 people worldwide. The Company is traded on the Nasdaq National Market under the symbol ACTL and is headquartered at 955 East Arques Avenue, Sunnyvale, Calif., 94086-4533. Telephone: 888-99-ACTEL (992-2835). Internet: http://www.actel.com
The Actel name and logo and Libero are trademarks of Actel Corporation. All other trademarks and servicemarks are the property of their respective owners.
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