Cadence and TSMC Announce Digital Flow Based on Cadence SoC Encounter

6/4/2002 - Cadence Design Systems, Inc. (NYSE:CDN) and Taiwan Semiconductor Manufacturing Company (TSMC) announced successful in-house design validation of a hierarchical digital flow allowing design engineers to devise complex, multi-million-gate system-on-a-chips (SoCs) for fabrication at TSMC. The Cadence® reference flow for TSMC comprises a Cadence-based hierarchical Verilog-to-GDSII design methodology with SoC Encounter for designers targeting TSMC 0.18-micron and below processes.

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