Synopsys Donates Key Verification Technologies to Accellera's SystemVerilog 3.1 Standard

6/11/2002 - Synopsys, Inc. (Nasdaq: SNPS), the technology leader for complex integrated circuit (IC) design, today announced its support for SystemVerilog 3.0 and donation of several technologies to Accellera for SystemVerilog version 3.1. Accellera drives electronic design automation (EDA) standards, which enhance a language-based design automation process. The donations include testbench modeling capabilities, OpenVera™ assertions, a C/C++ model interface and a coverage application programming interface (API) that provides links to coverage metrics. "Accellera welcomes Synopsys' donation and is thrilled with their involvement in Accellera's standardization process," said Vassilios Gerousis, technical coordinating committee chair at Accellera. "When leading EDA companies make strong technical donations to SystemVerilog, they not only make the language more robust, they support interoperable standards that allow the best EDA tools and methodologies to work seamlessly together. Synopsys was instrumental in making Verilog the de facto standard for RTL design. We look forward to working with Synopsys to lead the effort to do the same with SystemVerilog."

Previous Page | News by Category | News Search

If you found this page useful, bookmark and share it on: