Revolutionary New Databahn Core Solves Memory Bandwidth Bottleneck for SoC Designs

6/10/2002 - Denali Software, Inc., the leader in memory system design and verification, today announced its Databahn™ core for SoC bandwidth allocation, the first intellectual property core to dramatically reduce the time designers spend on developing and testing SoC memory systems. The configurable and programmable core manages and optimizes the memory access of multiple on-chip computing clients to the finite bandwidth of off-chip DRAM memory. Today’s SoC designs incorporate various RISC processors, DSP’s, and dedicated processors, all of which require high-bandwidth access to off-chip memory. Some access memory via on-chip interfaces such as AMBA® technology from ARM, while others interface memory via dedicated ports. SoC designers spend considerable time designing systems to allocate off-chip memory access to the various on-chip processing units—all based upon the unique bandwidth and latency requirements of individual processing units. The task is further complicated by the need to adjust the memory access to the processing elements during the design process, and the need to support new and emerging high-speed DRAMs such as DDR-SDRAM, FCRAM, and RLDRAM.

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