Floorplan Compiler dramatically reduces the time and iterations required to converge on high quality floorplans

6/10/2002 - Synopsys, Inc. (Nasdaq: SNPS), the technology leader for complex integrated circuit (IC) designs, today introduced Floorplan Compiler, a high-end hierarchical design planner that enables designers to save time and money by creating high quality floorplans in dramatically fewer iterations. Building an efficient hierarchical floorplan is typically difficult and time-consuming, requiring numerous iterations. Floorplan Compiler's virtual flat approach solves this problem by eliminating the ping-pong effect that normally occurs between chip-level and block-level floorplanning. The result is a product that enables all critical floorplanning decisions such as partitioning, block shaping, macro placement, pin assignment, and feed-through optimization to be made in the full context of the chip, including blockages and routing hotspots.

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