6/18/2002 - Armed with design tools from Cadence Design Systems, Inc. (NYSE: CDN), featuring NeoCell, Hitachi Ltd. has reduced the turnaround time needed for its most challenging analog RF IC physical designs with 0.25 BiCMOS process technology by approximately 30 percent. With Cadence and its distributor, Innotech Corporation, as preferred suppliers, Hitachi was able to achieve this significant improvement in design productivity by adopting Cadence® automated custom physical design methodology. Since the analog IP is captured as constraints in the schematic and can be re-used, Hitachi believes it will be able to reduce by 50 percent the time to generate derivative of physical designs -- providing a tremendous time-to-market advantage. Success was measured by design turnaround time, quality of results and the ability to reuse the design for future derivative products. The results generated from this new flow met all these criteria enabling Hitachi to tapeout their design earlier than expected.
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