Sequence Zero Simulation Key To Low-Power RTL Design

5/20/2002 - Sequence Design today announced the incorporation of new capabilities in PowerTheater™ that allow front-end designers to estimate power consumption at the RTL level using static vector-independent analysis, without test benches or simulation. Part of the company's NanoCool™ flow for low-power, low-voltage 100nm SoC design, PowerTheater's Zero-Sim, for "zero simulation," feature provides intelligent feedback on average power consumption early, and at successive iterations, to optimize power before freezing RTL code.

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