Synopsys LEDA 3.1 Delivers Full-Chip Mixed-Language Checking Capabilities

5/14/2002 - Synopsys, Inc. (Nasdaq: SNPS), the technology leader in complex integrated circuit (IC) design, today announced LEDA® 3.1, a programmable coding and design guideline checker that features full-chip, mixed-language checking capabilities to speed development of complex system-on-chip (SoC) designs. LEDA 3.1 adds prepackaged rules that help designers maximize the performance of Synopsys tools such as VCS, Formality® and Design Compiler. LEDA 3.1 also enables engineers to check their designs for compliance with reuse guidelines found in the Reuse Methodology Manual (RMM) and the DesignWare® style guide. In addition, it provides enhanced programmability for creating custom coding guidelines.

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