Synopsys' Physical Compiler Enables Timing Closure Flow

4/10/2002 - Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex integrated circuit (IC) design, today announced a new version of its premier physical synthesis tool, Physical Compiler 2002.02, which provides designers with a timing closure flow that scales to twenty million plus gate designs. There are three key capabilities introduced in this release of Physical Compiler that enable this high capacity flow: 64-bit platform support to more than double the practical capacity, Interface Logic Models, also supported by PrimeTime®, to extend its hierarchical chip level capacity, and a new quick mode that offers a 5X runtime improvement in a design exploration flow.

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